On Thu, Apr 7, 2022 at 1:36 AM Brad Larson <brad@xxxxxxxxxxx> wrote:
>
> Pensando Elba ARM 64-bit SoC is integrated with this IP and
> explicitly controls byte-lane enables resulting in an additional
> reg property resource.
>
> Signed-off-by: Brad Larson <brad@xxxxxxxxxxx>
> ---
> Change from V3:
> - Change from elba-emmc to elba-sd4hc to match file convention
> - Use minItems: 1 and maxItems: 2 to pass schema check
>
> Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml b/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml
> index 4207fed62dfe..278a71b27488 100644
> --- a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml
> +++ b/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml
> @@ -19,10 +19,12 @@ properties:
> - enum:
> - microchip,mpfs-sd4hc
> - socionext,uniphier-sd4hc
> + - pensando,elba-sd4hc
> - const: cdns,sd4hc
>
> reg:
> - maxItems: 1
> + minItems: 1
> + maxItems: 2
>
Shouldn't the binding describe what the register areas are? If there
is only one of them, it is fairly clear, but when you have the choice
between one and two, it gets ambiguous, and there is a risk that
another SoC might have a different register area in the second entry,
making it incompatible.
Arnd
