On Wed, 19 Jan 2022 at 08:54, Ben Chuang <benchuanggli@xxxxxxxxx> wrote:
>
> From: Ben Chuang <ben.chuang@xxxxxxxxxxxxxxxxxxx>
>
> Add a vendor-specific bit at the bit26 of GL9750's register 878h and
> GL9755's register 78h to decide whether to disable SSC function. If
> this bit is set, the SSC function will be disabled.
>
> Signed-off-by: Ben Chuang <ben.chuang@xxxxxxxxxxxxxxxxxxx>
Applied for next, thanks!
Kind regards
Uffe
> ---
> drivers/mmc/host/sdhci-pci-gli.c | 66 ++++++++++++++++++++++++++------
> 1 file changed, 54 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c
> index 9de3d91283af..b8cd7a365ec2 100644
> --- a/drivers/mmc/host/sdhci-pci-gli.c
> +++ b/drivers/mmc/host/sdhci-pci-gli.c
> @@ -62,6 +62,7 @@
> #define GLI_9750_MISC_RX_INV_OFF 0x0
> #define GLI_9750_MISC_RX_INV_VALUE GLI_9750_MISC_RX_INV_OFF
> #define GLI_9750_MISC_TX1_DLY_VALUE 0x5
> +#define SDHCI_GLI_9750_MISC_SSC_OFF BIT(26)
>
> #define SDHCI_GLI_9750_TUNING_CONTROL 0x540
> #define SDHCI_GLI_9750_TUNING_CONTROL_EN BIT(4)
> @@ -134,6 +135,9 @@
> #define PCI_GLI_9755_SerDes 0x70
> #define PCI_GLI_9755_SCP_DIS BIT(19)
>
> +#define PCI_GLI_9755_MISC 0x78
> +#define PCI_GLI_9755_MISC_SSC_OFF BIT(26)
> +
> #define GLI_MAX_TUNING_LOOP 40
>
> /* Genesys Logic chipset */
> @@ -368,6 +372,19 @@ static void gl9750_set_pll(struct sdhci_host *host, u8 dir, u16 ldiv, u8 pdiv)
> mdelay(1);
> }
>
> +static bool gl9750_ssc_enable(struct sdhci_host *host)
> +{
> + u32 misc;
> + u8 off;
> +
> + gl9750_wt_on(host);
> + misc = sdhci_readl(host, SDHCI_GLI_9750_MISC);
> + off = FIELD_GET(SDHCI_GLI_9750_MISC_SSC_OFF, misc);
> + gl9750_wt_off(host);
> +
> + return !off;
> +}
> +
> static void gl9750_set_ssc(struct sdhci_host *host, u8 enable, u8 step, u16 ppm)
> {
> u32 pll;
> @@ -389,22 +406,28 @@ static void gl9750_set_ssc(struct sdhci_host *host, u8 enable, u8 step, u16 ppm)
>
> static void gl9750_set_ssc_pll_205mhz(struct sdhci_host *host)
> {
> - /* set pll to 205MHz and enable ssc */
> - gl9750_set_ssc(host, 0x1, 0xF, 0x5A1D);
> + bool enable = gl9750_ssc_enable(host);
> +
> + /* set pll to 205MHz and ssc */
> + gl9750_set_ssc(host, enable, 0xF, 0x5A1D);
> gl9750_set_pll(host, 0x1, 0x246, 0x0);
> }
>
> static void gl9750_set_ssc_pll_100mhz(struct sdhci_host *host)
> {
> - /* set pll to 100MHz and enable ssc */
> - gl9750_set_ssc(host, 0x1, 0xE, 0x51EC);
> + bool enable = gl9750_ssc_enable(host);
> +
> + /* set pll to 100MHz and ssc */
> + gl9750_set_ssc(host, enable, 0xE, 0x51EC);
> gl9750_set_pll(host, 0x1, 0x244, 0x1);
> }
>
> static void gl9750_set_ssc_pll_50mhz(struct sdhci_host *host)
> {
> - /* set pll to 50MHz and enable ssc */
> - gl9750_set_ssc(host, 0x1, 0xE, 0x51EC);
> + bool enable = gl9750_ssc_enable(host);
> +
> + /* set pll to 50MHz and ssc */
> + gl9750_set_ssc(host, enable, 0xE, 0x51EC);
> gl9750_set_pll(host, 0x1, 0x244, 0x3);
> }
>
> @@ -529,6 +552,19 @@ static void gl9755_set_pll(struct pci_dev *pdev, u8 dir, u16 ldiv, u8 pdiv)
> mdelay(1);
> }
>
> +static bool gl9755_ssc_enable(struct pci_dev *pdev)
> +{
> + u32 misc;
> + u8 off;
> +
> + gl9755_wt_on(pdev);
> + pci_read_config_dword(pdev, PCI_GLI_9755_MISC, &misc);
> + off = FIELD_GET(PCI_GLI_9755_MISC_SSC_OFF, misc);
> + gl9755_wt_off(pdev);
> +
> + return !off;
> +}
> +
> static void gl9755_set_ssc(struct pci_dev *pdev, u8 enable, u8 step, u16 ppm)
> {
> u32 pll;
> @@ -550,22 +586,28 @@ static void gl9755_set_ssc(struct pci_dev *pdev, u8 enable, u8 step, u16 ppm)
>
> static void gl9755_set_ssc_pll_205mhz(struct pci_dev *pdev)
> {
> - /* set pll to 205MHz and enable ssc */
> - gl9755_set_ssc(pdev, 0x1, 0xF, 0x5A1D);
> + bool enable = gl9755_ssc_enable(pdev);
> +
> + /* set pll to 205MHz and ssc */
> + gl9755_set_ssc(pdev, enable, 0xF, 0x5A1D);
> gl9755_set_pll(pdev, 0x1, 0x246, 0x0);
> }
>
> static void gl9755_set_ssc_pll_100mhz(struct pci_dev *pdev)
> {
> - /* set pll to 100MHz and enable ssc */
> - gl9755_set_ssc(pdev, 0x1, 0xE, 0x51EC);
> + bool enable = gl9755_ssc_enable(pdev);
> +
> + /* set pll to 100MHz and ssc */
> + gl9755_set_ssc(pdev, enable, 0xE, 0x51EC);
> gl9755_set_pll(pdev, 0x1, 0x244, 0x1);
> }
>
> static void gl9755_set_ssc_pll_50mhz(struct pci_dev *pdev)
> {
> - /* set pll to 50MHz and enable ssc */
> - gl9755_set_ssc(pdev, 0x1, 0xE, 0x51EC);
> + bool enable = gl9755_ssc_enable(pdev);
> +
> + /* set pll to 50MHz and ssc */
> + gl9755_set_ssc(pdev, enable, 0xE, 0x51EC);
> gl9755_set_pll(pdev, 0x1, 0x244, 0x3);
> }
>
> --
> 2.34.1
>
