Hi!
The ARTPEC-8 SoC has a DWMMC controller that is compatible with the
Exynos 7 version v2.70a. The main differences from Exynos 7 is that it
does not support HS400 and has an extended data read timeout. To run
this controller we need to add compatibility for ARTPEC-8, because we
need to separate the configuration of the TMOUT register from the non
ARTPEC-8 versions.
This patchset is dependent on 2 changes that has been added to the mmc
git next branch, but has not yet been merged to mainline:
Patch 2 of this patchset depends on commit 0e6f2c4c2072b ("mmc: dw_mmc:
add common capabilities to replace caps").
Patch 3 of this patchset depends on commit d5bc33487eab3 ("mmc: dw_mmc:
Allow lower TMOUT value than maximum").
Kind regards
Mårten Lindahl
Changes in v2:
- Change compatible string vendor prefix
- Removed unnecessary comment
- Change 1<<0 to BIT(0)
Changes in v3:
- Add callback for implementation specific control of data timeout
- Add callback for implementation specific read of cycle count for
data timeout.
- Move definition of DW_MMC_QUIRK_EXTENDED_TMOUT from patch 3/4 to
patch 4/4.
Mårten Lindahl (4):
dt-bindings: mmc: exynos-dw-mshc: Add support for ARTPEC-8
mmc: dw_mmc-exynos: Add support for ARTPEC-8
mmc: dw_mmc: Add driver callbacks for data read timeout
mmc: dw_mmc: Do not wait for DTO in case of error
.../bindings/mmc/exynos-dw-mshc.txt | 2 +
drivers/mmc/host/dw_mmc-exynos.c | 101 ++++++++++++++++--
drivers/mmc/host/dw_mmc.c | 21 +++-
drivers/mmc/host/dw_mmc.h | 10 ++
4 files changed, 122 insertions(+), 12 deletions(-)
--
2.20.1
