Re: [RFC PATCH v2 03/21] clk: renesas: r8a779a0: add SDnH clock to V3U

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

 



CC clk

On Wed, Nov 10, 2021 at 8:16 PM Wolfram Sang
<wsa+renesas@xxxxxxxxxxxxxxxxxxxx> wrote:
> Currently a pass-through clock but we will make it a real divider clock
> in the next patches.
>
> Signed-off-by: Wolfram Sang <wsa+renesas@xxxxxxxxxxxxxxxxxxxx>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
> ---
> Changes since RFC v1:
> * added tag from Geert
>
>  drivers/clk/renesas/r8a779a0-cpg-mssr.c | 11 ++++++++++-
>  1 file changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
> index f16d125ca009..fb7f0cf2654a 100644
> --- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
> @@ -33,6 +33,7 @@ enum rcar_r8a779a0_clk_types {
>         CLK_TYPE_R8A779A0_PLL1,
>         CLK_TYPE_R8A779A0_PLL2X_3X,     /* PLL[23][01] */
>         CLK_TYPE_R8A779A0_PLL5,
> +       CLK_TYPE_R8A779A0_SDH,
>         CLK_TYPE_R8A779A0_SD,
>         CLK_TYPE_R8A779A0_MDSEL,        /* Select parent/divider using mode pin */
>         CLK_TYPE_R8A779A0_OSC,  /* OSC EXTAL predivider and fixed divider */
> @@ -84,6 +85,9 @@ enum clk_ids {
>         DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_PLL2X_3X, CLK_MAIN, \
>                  .offset = _offset)
>
> +#define DEF_SDH(_name, _id, _parent, _offset)   \
> +       DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_SDH, _parent, .offset = _offset)
> +
>  #define DEF_SD(_name, _id, _parent, _offset)   \
>         DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_SD, _parent, .offset = _offset)
>
> @@ -145,7 +149,8 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
>         DEF_FIXED("cp",         R8A779A0_CLK_CP,        CLK_EXTAL,      2, 1),
>         DEF_FIXED("cl16mck",    R8A779A0_CLK_CL16MCK,   CLK_PLL1_DIV2,  64, 1),
>
> -       DEF_SD("sd0",           R8A779A0_CLK_SD0,       CLK_SDSRC,      0x870),
> +       DEF_SDH("sdh0",         R8A779A0_CLK_SD0H,      CLK_SDSRC,         0x870),
> +       DEF_SD( "sd0",          R8A779A0_CLK_SD0,       R8A779A0_CLK_SD0H, 0x870),
>
>         DEF_DIV6P1("mso",       R8A779A0_CLK_MSO,       CLK_PLL5_DIV4,  0x87c),
>         DEF_DIV6P1("canfd",     R8A779A0_CLK_CANFD,     CLK_PLL5_DIV4,  0x878),
> @@ -293,6 +298,10 @@ static struct clk * __init rcar_r8a779a0_cpg_clk_register(struct device *dev,
>                 div = cpg_pll_config->pll5_div;
>                 break;
>
> +       case CLK_TYPE_R8A779A0_SDH:
> +               return cpg_sdh_clk_register(core->name, base + core->offset,
> +                                          __clk_get_name(parent), notifiers);
> +
>         case CLK_TYPE_R8A779A0_SD:
>                 return cpg_sd_clk_register(core->name, base, core->offset,
>                                            __clk_get_name(parent), notifiers,
> --
> 2.30.2



[Index of Archives]     [Linux Memonry Technology]     [Linux USB Devel]     [Linux Media]     [Video for Linux]     [Linux Audio Users]     [Yosemite News]     [Linux Kernel]     [Linux SCSI]

  Powered by Linux