Hi NXP S32 and i.MX Linux teams,
On Thu, Oct 21, 2021 at 03:13:32PM +0800, Chester Lin wrote:
> Support the SDHCI controller found on NXP S32G2 platform. The new flag
> ESDHC_FLAG_SKIP_ERR004536 is used because the hardware erratum bit is not
> applicable for S32G2.
>
> Signed-off-by: Chester Lin <clin@xxxxxxxx>
> ---
> drivers/mmc/host/sdhci-esdhc-imx.c | 17 +++++++++++++++--
> 1 file changed, 15 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
> index f18d169bc8ff..d0f7d46a0354 100644
> --- a/drivers/mmc/host/sdhci-esdhc-imx.c
> +++ b/drivers/mmc/host/sdhci-esdhc-imx.c
> @@ -196,6 +196,9 @@
> */
> #define ESDHC_FLAG_BROKEN_AUTO_CMD23 BIT(16)
>
> +/* ERR004536 is not applicable for the IP */
> +#define ESDHC_FLAG_SKIP_ERR004536 BIT(17)
> +
> enum wp_types {
> ESDHC_WP_NONE, /* no WP, neither controller nor gpio */
> ESDHC_WP_CONTROLLER, /* mmc controller internal WP */
> @@ -289,6 +292,13 @@ static const struct esdhc_soc_data usdhc_imx7d_data = {
> | ESDHC_FLAG_BROKEN_AUTO_CMD23,
> };
>
> +static struct esdhc_soc_data usdhc_s32g2_data = {
> + .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING
> + | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
> + | ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES
> + | ESDHC_FLAG_SKIP_ERR004536,
> +};
> +
> static struct esdhc_soc_data usdhc_imx7ulp_data = {
> .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
> | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
> @@ -347,6 +357,7 @@ static const struct of_device_id imx_esdhc_dt_ids[] = {
> { .compatible = "fsl,imx7ulp-usdhc", .data = &usdhc_imx7ulp_data, },
> { .compatible = "fsl,imx8qxp-usdhc", .data = &usdhc_imx8qxp_data, },
> { .compatible = "fsl,imx8mm-usdhc", .data = &usdhc_imx8mm_data, },
> + { .compatible = "nxp,s32g2-usdhc", .data = &usdhc_s32g2_data, },
> { /* sentinel */ }
> };
> MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids);
> @@ -1359,8 +1370,10 @@ static void sdhci_esdhc_imx_hwinit(struct sdhci_host *host)
> * erratum ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL
> * TO1.1, it's harmless for MX6SL
> */
> - writel(readl(host->ioaddr + 0x6c) & ~BIT(7),
> - host->ioaddr + 0x6c);
> + if (!(imx_data->socdata->flags & ESDHC_FLAG_SKIP_ERR004536)) {
> + writel(readl(host->ioaddr + 0x6c) & ~BIT(7),
> + host->ioaddr + 0x6c);
> + }
Hope you don't might that I raise this question here. Is it really necessary
to unconditionally apply the erratum bit even if some SoCs might not need this
workaround? From the S32 implementation in CodeAurora[1], I noticed that this
bit is not required by S32V/S32G so I wonder if there's any better way to
refine this part?
Thanks,
Chester
[1] https://source.codeaurora.org/external/autobsps32/linux/tree/drivers/mmc/host/sdhci-esdhc-imx.c?h=release/bsp30.0-5.4-rt#n1268
>
> /* disable DLL_CTRL delay line settings */
> writel(0x0, host->ioaddr + ESDHC_DLL_CTRL);
> --
> 2.30.0
>
