On 12/09/2021 22:08, Dmitry Osipenko wrote: > Document new OPP table and power domain properties of the video decoder > hardware. > > Reviewed-by: Rob Herring <robh@xxxxxxxxxx> > Signed-off-by: Dmitry Osipenko <digetx@xxxxxxxxx> Acked-by: Hans Verkuil <hverkuil-cisco@xxxxxxxxx> Regards, Hans > --- > .../devicetree/bindings/media/nvidia,tegra-vde.yaml | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/Documentation/devicetree/bindings/media/nvidia,tegra-vde.yaml b/Documentation/devicetree/bindings/media/nvidia,tegra-vde.yaml > index 3b6c1f031e04..0b7d4d815707 100644 > --- a/Documentation/devicetree/bindings/media/nvidia,tegra-vde.yaml > +++ b/Documentation/devicetree/bindings/media/nvidia,tegra-vde.yaml > @@ -68,6 +68,16 @@ properties: > description: > Phandle of the SRAM MMIO node. > > + operating-points-v2: > + description: > + Should contain freqs and voltages and opp-supported-hw property, > + which is a bitfield indicating SoC speedo or process ID mask. > + > + power-domains: > + maxItems: 1 > + description: > + Phandle to the SoC core power domain. > + > required: > - compatible > - reg > @@ -104,4 +114,6 @@ examples: > reset-names = "vde", "mc"; > resets = <&rst 61>, <&mem 13>; > iommus = <&mem 15>; > + operating-points-v2 = <&dvfs_opp_table>; > + power-domains = <&domain>; > }; >
