On Wed, 28 Apr 2021 14:50:02 +0100,
<cl@xxxxxxxxxxxxxx> wrote:
>
> From: Liang Chen <cl@xxxxxxxxxxxxxx>
>
> RK3568 is a high-performance and low power quad-core application processor
> designed for personal mobile internet device and AIoT equipment. This patch
> add basic core dtsi file for it.
>
> We use scmi_clk for cortex-a55 instead of standard ARMCLK, so that
> kernel/uboot/rtos can change cpu clk with the same code in ATF, and we will
> enalbe a special high-performance PLL when high frequency is required. The
> smci_clk code is in ATF, and clkid for cpu is 0, as below:
>
> cpu0: cpu@0 {
> device_type = "cpu";
> compatible = "arm,cortex-a55";
> reg = <0x0 0x0>;
> clocks = <&scmi_clk 0>;
> };
>
> Signed-off-by: Liang Chen <cl@xxxxxxxxxxxxxx>
> ---
> .../boot/dts/rockchip/rk3568-pinctrl.dtsi | 3111 +++++++++++++++++
> arch/arm64/boot/dts/rockchip/rk3568.dtsi | 779 +++++
> 2 files changed, 3890 insertions(+)
> create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi
> create mode 100644 arch/arm64/boot/dts/rockchip/rk3568.dtsi
[...]
> + gic: interrupt-controller@fd400000 {
> + compatible = "arm,gic-v3";
> + reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
> + <0x0 0xfd460000 0 0xc0000>; /* GICR */
If this SoC has 4 CPUs, that's 4 redistributors. Given that GIC600
doesn't implement VLPIs, that's 128kB per redistributors. Why is GICR
large enough for 6 CPUs here? Is that copy-pasted from another SoC?
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + mbi-alias = <0x0 0xfd400000>;
> + mbi-ranges = <296 24>;
> + msi-controller;
> + };
Glad to see that you found some spare SPIs to get MSIs going
However, the whole point of mbi-alias (aka GICA in GIC600) is to be
different from GICD and provide some isolation via an IOMMU. If I
trust the TRM, if should be at 0xfd10000 in your implementation.
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
