Hi again, On Wed, 2021-04-07 at 16:37 -0400, Alan Cooper wrote: > Nicolas, > > I got a better description of the failure and it looks like the bus > clock needs to be limited to 300KHz for a 500MHz core clock. > What's happening is that an internal reset sequence is needed after a > command timeout and the reset signal needs to be asserted for at least > 2 ticks of the bus clock. This is done using a 12 bit counter clocked > by the core clock. That means a 500MHz core clock produces a 122KHz > reset signal which is too fast for 2 ticks of the 200KHz bus clock > (100KHz) but is okay for the 300KHz (150Khz) bus clock. Is there any value in implementing this in a generic way? That is, will a SoC other than BCM2711 ever need this? Otherwise I can simply limit BCM2711's sdhci-iproc min clk frequency to 300KHz and call it a day. The alternative is something the likes of: min_clk = clk_get_rate(core_bus) >> 11; But it involves updating the bindings and DT. Regards, Nicolas
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