On Wed, 6 Jan 2021 at 10:27, Renius Chen <reniuschengl@xxxxxxxxx> wrote: > > The R/W performance of GL9763E is low with some platforms, which > support ASPM mechanism, due to entering L1 state very frequently > in R/W process. Enlarge its ASPM L1 entry delay to improve the > R/W performance of GL9763E. What do you mean by frequently? In between a burst of request or during a burst of request? I am thinking that this could have an effect on energy instead, but I guess it's not always straightforward to decide what's most important. Anyway, what does it mean when you change to use 0x3FF? Are you increasing the idle period? Then for how long? Kind regards Uffe > > Signed-off-by: Renius Chen <reniuschengl@xxxxxxxxx> > --- > drivers/mmc/host/sdhci-pci-gli.c | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c > index c6a107d7c742..2d13bfcbcacf 100644 > --- a/drivers/mmc/host/sdhci-pci-gli.c > +++ b/drivers/mmc/host/sdhci-pci-gli.c > @@ -88,6 +88,10 @@ > #define PCIE_GLI_9763E_SCR 0x8E0 > #define GLI_9763E_SCR_AXI_REQ BIT(9) > > +#define PCIE_GLI_9763E_CFG2 0x8A4 > +#define GLI_9763E_CFG2_L1DLY GENMASK(28, 19) > +#define GLI_9763E_CFG2_L1DLY_MAX 0x3FF > + > #define PCIE_GLI_9763E_MMC_CTRL 0x960 > #define GLI_9763E_HS400_SLOW BIT(3) > > @@ -792,6 +796,11 @@ static void gli_set_gl9763e(struct sdhci_pci_slot *slot) > value &= ~GLI_9763E_HS400_SLOW; > pci_write_config_dword(pdev, PCIE_GLI_9763E_MMC_CTRL, value); > > + pci_read_config_dword(pdev, PCIE_GLI_9763E_CFG2, &value); > + value &= ~GLI_9763E_CFG2_L1DLY; > + value |= FIELD_PREP(GLI_9763E_CFG2_L1DLY, GLI_9763E_CFG2_L1DLY_MAX); > + pci_write_config_dword(pdev, PCIE_GLI_9763E_CFG2, value); > + > pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value); > value &= ~GLI_9763E_VHS_REV; > value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_R); > -- > 2.27.0 >
