Hi Ulf,
On Wed, Nov 25, 2020 at 6:04 PM Ulf Hansson <ulf.hansson@xxxxxxxxxx> wrote:
>
> On Wed, 25 Nov 2020 at 10:59, Ben Chuang <benchuanggli@xxxxxxxxx> wrote:
> >
> > From: Ben Chuang <ben.chuang@xxxxxxxxxxxxxxxxxxx>
> >
> > The GL9763E uses 150Mhz (slow mode) by default in HS400 mode. In order
> > to make HS400 mode run at 200Mhz, the slow mode needs to be turned off.
> >
> > Fixes: 1ae1d2d6e555 ("mmc: sdhci-pci-gli: Add Genesys Logic GL9763E support")
>
> Why a fixes tag? This patch looks like an improvement and not a fix, right?
>
Since the specification defines that the HS400 mode must run at 200Mhz,
this patch fixes the HS400 mode to 200Mhz.
Best regards,
Ben
> Kind regards
> Uffe
>
> > Signed-off-by: Ben Chuang <ben.chuang@xxxxxxxxxxxxxxxxxxx>
> > ---
> > drivers/mmc/host/sdhci-pci-gli.c | 7 +++++++
> > 1 file changed, 7 insertions(+)
> >
> > diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c
> > index 9887485a4134..d45d7e529150 100644
> > --- a/drivers/mmc/host/sdhci-pci-gli.c
> > +++ b/drivers/mmc/host/sdhci-pci-gli.c
> > @@ -87,6 +87,9 @@
> > #define PCIE_GLI_9763E_SCR 0x8E0
> > #define GLI_9763E_SCR_AXI_REQ BIT(9)
> >
> > +#define PCIE_GLI_9763E_MMC_CTRL 0x960
> > +#define GLI_9763E_HS400_SLOW BIT(3)
> > +
> > #define SDHCI_GLI_9763E_CQE_BASE_ADDR 0x200
> > #define GLI_9763E_CQE_TRNS_MODE (SDHCI_TRNS_MULTI | \
> > SDHCI_TRNS_BLK_CNT_EN | \
> > @@ -764,6 +767,10 @@ static void gli_set_gl9763e(struct sdhci_pci_slot *slot)
> > value |= GLI_9763E_SCR_AXI_REQ;
> > pci_write_config_dword(pdev, PCIE_GLI_9763E_SCR, value);
> >
> > + pci_read_config_dword(pdev, PCIE_GLI_9763E_MMC_CTRL, &value);
> > + value &= ~GLI_9763E_HS400_SLOW;
> > + pci_write_config_dword(pdev, PCIE_GLI_9763E_MMC_CTRL, value);
> > +
> > pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value);
> > value &= ~GLI_9763E_VHS_REV;
> > value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_R);
> > --
> > 2.29.2
> >
