+Marek On 10. 11. 20 18:42, Manish Narani wrote: > Allow configuring the Output and Input tap values with zero to avoid > failures in some cases (one of them is SD boot mode) where the output > and input tap values may be already set to non-zero. > > Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xxxxxxxxxx> > Signed-off-by: Manish Narani <manish.narani@xxxxxxxxxx> > --- > drivers/mmc/host/sdhci-of-arasan.c | 40 ++++++------------------------ > 1 file changed, 8 insertions(+), 32 deletions(-) > > diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c > index 829ccef87426..100621e55427 100644 > --- a/drivers/mmc/host/sdhci-of-arasan.c > +++ b/drivers/mmc/host/sdhci-of-arasan.c > @@ -600,14 +600,8 @@ static int sdhci_zynqmp_sdcardclk_set_phase(struct clk_hw *hw, int degrees) > u8 tap_delay, tap_max = 0; > int ret; > > - /* > - * This is applicable for SDHCI_SPEC_300 and above > - * ZynqMP does not set phase for <=25MHz clock. > - * If degrees is zero, no need to do anything. > - */ > - if (host->version < SDHCI_SPEC_300 || > - host->timing == MMC_TIMING_LEGACY || > - host->timing == MMC_TIMING_UHS_SDR12 || !degrees) > + /* This is applicable for SDHCI_SPEC_300 and above */ > + if (host->version < SDHCI_SPEC_300) > return 0; > > switch (host->timing) { > @@ -668,14 +662,8 @@ static int sdhci_zynqmp_sampleclk_set_phase(struct clk_hw *hw, int degrees) > u8 tap_delay, tap_max = 0; > int ret; > > - /* > - * This is applicable for SDHCI_SPEC_300 and above > - * ZynqMP does not set phase for <=25MHz clock. > - * If degrees is zero, no need to do anything. > - */ > - if (host->version < SDHCI_SPEC_300 || > - host->timing == MMC_TIMING_LEGACY || > - host->timing == MMC_TIMING_UHS_SDR12 || !degrees) > + /* This is applicable for SDHCI_SPEC_300 and above */ > + if (host->version < SDHCI_SPEC_300) > return 0; > > switch (host->timing) { > @@ -733,14 +721,8 @@ static int sdhci_versal_sdcardclk_set_phase(struct clk_hw *hw, int degrees) > struct sdhci_host *host = sdhci_arasan->host; > u8 tap_delay, tap_max = 0; > > - /* > - * This is applicable for SDHCI_SPEC_300 and above > - * Versal does not set phase for <=25MHz clock. > - * If degrees is zero, no need to do anything. > - */ > - if (host->version < SDHCI_SPEC_300 || > - host->timing == MMC_TIMING_LEGACY || > - host->timing == MMC_TIMING_UHS_SDR12 || !degrees) > + /* This is applicable for SDHCI_SPEC_300 and above */ > + if (host->version < SDHCI_SPEC_300) > return 0; > > switch (host->timing) { > @@ -804,14 +786,8 @@ static int sdhci_versal_sampleclk_set_phase(struct clk_hw *hw, int degrees) > struct sdhci_host *host = sdhci_arasan->host; > u8 tap_delay, tap_max = 0; > > - /* > - * This is applicable for SDHCI_SPEC_300 and above > - * Versal does not set phase for <=25MHz clock. > - * If degrees is zero, no need to do anything. > - */ > - if (host->version < SDHCI_SPEC_300 || > - host->timing == MMC_TIMING_LEGACY || > - host->timing == MMC_TIMING_UHS_SDR12 || !degrees) > + /* This is applicable for SDHCI_SPEC_300 and above */ > + if (host->version < SDHCI_SPEC_300) > return 0; > > switch (host->timing) { >