MT8192 mmc host ip is compatible with MT8183.
Add support for this.
Signed-off-by: Wenbin Mei <wenbin.mei@xxxxxxxxxxxx>
Reviewed-by: Ulf Hansson <ulf.hansson@xxxxxxxxxx>
---
Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 15 +++++++++++++--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
index 2d5ab1411cd5..f12a44f3e6c4 100644
--- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
+++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
@@ -18,6 +18,9 @@ properties:
- const: mediatek,mt8135-mmc
- const: mediatek,mt8173-mmc
- const: mediatek,mt8183-mmc
+ - items:
+ - const: mediatek,mt8192-mmc
+ - const: mediatek,mt8183-mmc
- const: mediatek,mt8516-mmc
- const: mediatek,mt6779-mmc
- const: mediatek,mt2701-mmc
@@ -43,21 +46,29 @@ properties:
description:
Should contain phandle for the clock feeding the MMC controller.
minItems: 2
- maxItems: 4
+ maxItems: 8
items:
- description: source clock (required).
- description: HCLK which used for host (required).
- description: independent source clock gate (required for MT2712).
- description: bus clock used for internal register access (required for MT2712 MSDC0/3).
+ - description: msdc subsys clock gate (required for MT8192).
+ - description: peripheral bus clock gate (required for MT8192).
+ - description: AXI bus clock gate (required for MT8192).
+ - description: AHB bus clock gate (required for MT8192).
clock-names:
minItems: 2
- maxItems: 4
+ maxItems: 8
items:
- const: source
- const: hclk
- const: source_cg
- const: bus_clk
+ - const: sys_cg
+ - const: pclk_cg
+ - const: axi_cg
+ - const: ahb_cg
pinctrl-names:
items:
--
2.18.0
