On Tue, 26 May 2020 at 12:32, <haibo.chen@xxxxxxx> wrote:
>
> From: Haibo Chen <haibo.chen@xxxxxxx>
>
> According the RM, the bit[6~0] of register ESDHC_TUNING_CTRL is
> TUNING_START_TAP, bit[7] of this register is to disable the command
> CRC check for standard tuning. So fix it here.
>
> Fixes: d87fc9663688 ("mmc: sdhci-esdhc-imx: support setting tuning start point")
> Signed-off-by: Haibo Chen <haibo.chen@xxxxxxx>
Applied for next, thanks!
Should we add a stable tag or it doesn't matter?
Kind regards
Uffe
> ---
> drivers/mmc/host/sdhci-esdhc-imx.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
> index 7af9d87d4245..2cf7fa59270e 100644
> --- a/drivers/mmc/host/sdhci-esdhc-imx.c
> +++ b/drivers/mmc/host/sdhci-esdhc-imx.c
> @@ -90,7 +90,7 @@
> #define ESDHC_STD_TUNING_EN (1 << 24)
> /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
> #define ESDHC_TUNING_START_TAP_DEFAULT 0x1
> -#define ESDHC_TUNING_START_TAP_MASK 0xff
> +#define ESDHC_TUNING_START_TAP_MASK 0x7f
> #define ESDHC_TUNING_STEP_MASK 0x00070000
> #define ESDHC_TUNING_STEP_SHIFT 16
>
> --
> 2.17.1
>
