On 17/04/20 4:55 pm, Alan Cooper wrote: > Acked-by: Al Cooper <alcooperx@xxxxxxxxx>On Thu, Apr 16, 2020 at 4:27 > AM Adrian Hunter <adrian.hunter@xxxxxxxxx> wrote: >> >> On 15/04/20 7:28 pm, Michał Mirosław wrote: >>> On Wed, Apr 15, 2020 at 03:25:52PM +0300, Adrian Hunter wrote: >>>> On 2/04/20 2:54 pm, Michał Mirosław wrote: >>>>> Fixed commit added an unnecessary read of CLOCK_CONTROL. The value read >>>>> is overwritten for programmable clock preset, but is carried over for >>>>> divided clock preset. This can confuse sdhci_enable_clk() if the register >>>>> has enable bits set for some reason at time time of clock calculation. >>>>> value to be ORed with enable flags. Remove the read. >>>> >>>> The read is not needed, but drivers usually manage the enable bits, >>>> especially disabling the clock before changing the frequency. What driver >>>> is it? >>> >>> Hopefully no driver requires this. It's just removing a trap. >> >> The only driver that looks like it would benefit is sdhci-brcmstb because it >> does not clear enable bits in sdhci_brcmstb_set_clock(). Adding Al Cooper. >> Al, can you ack this? > > sdhci_brcmstb_set_clock() assumed that sdhci_calc_clk() would always > return the divider value without the enable set, so this fixes a case > for DDR52 where the enable was not being cleared when the divider > value was changed. > Acked-by: Al Cooper <alcooperx@xxxxxxxxx> > That is good to know. The commit message needs to be updated with that information, otherwise: Acked-by: Adrian Hunter <adrian.hunter@xxxxxxxxx>
