On Thu, 12 Mar 2020 at 12:01, Masahiro Yamada
<yamada.masahiro@xxxxxxxxxxxxx> wrote:
>
> Use the FIELD_GET macro to get access to the register fields.
> Delete the shift macros.
>
> Signed-off-by: Masahiro Yamada <yamada.masahiro@xxxxxxxxxxxxx>
Applied for next, thanks!
Kind regards
Uffe
> ---
>
> drivers/mmc/host/sdhci.c | 10 +++++-----
> drivers/mmc/host/sdhci.h | 10 ++++------
> 2 files changed, 9 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
> index 63db84481dff..aec6692615c8 100644
> --- a/drivers/mmc/host/sdhci.c
> +++ b/drivers/mmc/host/sdhci.c
> @@ -9,6 +9,7 @@
> * - JMicron (hardware and technical support)
> */
>
> +#include <linux/bitfield.h>
> #include <linux/delay.h>
> #include <linux/dmaengine.h>
> #include <linux/ktime.h>
> @@ -1766,10 +1767,9 @@ u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
>
> clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
> pre_val = sdhci_get_preset_value(host);
> - div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
> - >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
> + div = FIELD_GET(SDHCI_PRESET_SDCLK_FREQ_MASK, pre_val);
> if (host->clk_mul &&
> - (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
> + (pre_val & SDHCI_PRESET_CLKGEN_SEL)) {
> clk = SDHCI_PROG_CLOCK_MODE;
> real_div = div + 1;
> clk_mul = host->clk_mul;
> @@ -2227,8 +2227,8 @@ void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
>
> sdhci_enable_preset_value(host, true);
> preset = sdhci_get_preset_value(host);
> - ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
> - >> SDHCI_PRESET_DRV_SHIFT;
> + ios->drv_type = FIELD_GET(SDHCI_PRESET_DRV_MASK,
> + preset);
> }
>
> /* Re-enable SD Clock */
> diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
> index a6a3ddcf97e7..abdcefee24cb 100644
> --- a/drivers/mmc/host/sdhci.h
> +++ b/drivers/mmc/host/sdhci.h
> @@ -9,6 +9,7 @@
> #ifndef __SDHCI_HW_H
> #define __SDHCI_HW_H
>
> +#include <linux/bits.h>
> #include <linux/scatterlist.h>
> #include <linux/compiler.h>
> #include <linux/types.h>
> @@ -267,12 +268,9 @@
> #define SDHCI_PRESET_FOR_SDR104 0x6C
> #define SDHCI_PRESET_FOR_DDR50 0x6E
> #define SDHCI_PRESET_FOR_HS400 0x74 /* Non-standard */
> -#define SDHCI_PRESET_DRV_MASK 0xC000
> -#define SDHCI_PRESET_DRV_SHIFT 14
> -#define SDHCI_PRESET_CLKGEN_SEL_MASK 0x400
> -#define SDHCI_PRESET_CLKGEN_SEL_SHIFT 10
> -#define SDHCI_PRESET_SDCLK_FREQ_MASK 0x3FF
> -#define SDHCI_PRESET_SDCLK_FREQ_SHIFT 0
> +#define SDHCI_PRESET_DRV_MASK GENMASK(15, 14)
> +#define SDHCI_PRESET_CLKGEN_SEL BIT(10)
> +#define SDHCI_PRESET_SDCLK_FREQ_MASK GENMASK(9, 0)
>
> #define SDHCI_SLOT_INT_STATUS 0xFC
>
> --
> 2.17.1
>
