Re: [PATCH] mmc: sdhci-of-esdhc: fix transfer mode register reading

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On Fri, 17 Jan 2020 at 07:41, Yangbo Lu <yangbo.lu@xxxxxxx> wrote:
>
> The standard SD controller uses two 16-bit registers for
> command sending.
> 0xC: Transfer Mode Register
> 0xE: Command Register
>
> But the eSDHC controller uses one 32-bit register instead.
> 0xC: XFERTYPE
>
> For Transfer Mode Register and Command Register writing,
> the eSDHC driver will store Transfer Mode Register value in
> a variable first. When Command Register writing happens,
> driver will directly write a 32-bit value into XFERTYPE
> register.
>
> But for Transfer Mode Register reading, driver just returns
> a actual value. This may cause issue for some read-modify-write
> operations. We should make both reading and write on that variable
> for Transfer Mode Register.
>
> Signed-off-by: Yangbo Lu <yangbo.lu@xxxxxxx>

Applied for next, thanks!

Kind regards
Uffe


> ---
>  drivers/mmc/host/sdhci-of-esdhc.c | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/drivers/mmc/host/sdhci-of-esdhc.c b/drivers/mmc/host/sdhci-of-esdhc.c
> index 8c06017..3ef4973 100644
> --- a/drivers/mmc/host/sdhci-of-esdhc.c
> +++ b/drivers/mmc/host/sdhci-of-esdhc.c
> @@ -173,6 +173,9 @@ static u16 esdhc_readw_fixup(struct sdhci_host *host,
>         u16 ret;
>         int shift = (spec_reg & 0x2) * 8;
>
> +       if (spec_reg == SDHCI_TRANSFER_MODE)
> +               return pltfm_host->xfer_mode_shadow;
> +
>         if (spec_reg == SDHCI_HOST_VERSION)
>                 ret = value & 0xffff;
>         else
> --
> 2.7.4
>



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