On Tue, Sep 17, 2019 at 10:43:35AM -0300, Fabio Estevam wrote: > On Tue, Sep 17, 2019 at 10:33 AM Russell King - ARM Linux admin > <linux@xxxxxxxxxxxxxxx> wrote: > > > That attempts to set bit 12 of the host control register 2 (0x3e). > > The LX2160A documentation states that bit 28 of 0x3c (they're 32-bit > > wide registers there) is "reserved". > > > > So, you're asking for a documented reserved bit to be set... > > Correct, v4 is not supported here indeed. > > From the LX2160 doc: > "Conforms to the SD Host Controller Standard Specification version 3.0" The pressing question seems to be this: Are the eSDHC on the LX2160A DMA coherent or are they not? Any chances of finding out internally what the true answer to that, rather than me poking about trying stuff experimentally? Having a definitive answer for a potentially data-corrupting change would be really good... -- RMK's Patch system: https://www.armlinux.org.uk/developer/patches/ FTTC broadband for 0.8mile line in suburbia: sync at 12.1Mbps down 622kbps up According to speedtest.net: 11.9Mbps down 500kbps up
