El 27/8/19 a las 15:24, Ulf Hansson escribió:> Assuming this should go stable as well? Perhaps you can find a > relevant commit that we can put as a fixes tag as well? > > Kind regards > Uffe The most relevant commit I've found that is related to enabling DDR speeds on H6 boards is this one: https://github.com/torvalds/linux/commit/07bafc1e3536a4e3c422dbd13341688b54f159bb . But it doesn't address the H6 SoC specifically, so I doubted whether it would be appropiate to mark this patch as fixing it, and opted to not do it. I don't mind adding that tag if it's appropiate, though :-) On the other hand, I'm not sure that I understood correctly what do you mean by this patch going stable, but I might say the changes themselves are stable and work. The only downside I can think of to them is that they are a kind of workaround that reduces performance on H6 boards and/or eMMC not affected by this problem (are there any?), unless device trees are changed. El 27/8/19 a las 15:32, Maxime Ripard escribió: > On Sun, Aug 25, 2019 at 05:05:58PM +0200, Alejandro González wrote: >> Some Allwinner H6 boards have timing problems when dealing with >> DDR-capable eMMC cards. These boards include the Pine H64 and Tanix TX6. >> >> These timing problems result in out of sync communication between the >> driver and the eMMC, which renders the memory unsuable for every >> operation but some basic commmands, like reading the status register. >> >> The cause of these timing problems is not yet well known, but they go >> away by disabling DDR mode operation in the driver. Like on some H5 >> boards, it might be that the traces are not precise enough to support >> these speeds. However, Jernej Skrabec compared the BSP driver with this >> driver, and found that the BSP driver configures pinctrl to operate at >> 1.8 V when entering DDR mode (although 3.3 V operation is supported), while >> the mainline kernel lacks any mechanism to switch voltages dynamically. >> Finally, other possible cause might be some timing parameter that is >> different on the H6 with respect to other SoCs. > > This should be a comment in the driver where this is disabled. > > Maxime Thank you for your review. I'll mention that briefly in a comment in the code for the next revision of this patch. Regards.
