> > > > ddr_signaling is set to true for DDR50 and DDR52 modes but is not > > set back to false for other modes. This programs incorrect host > > clock when mode change happens from DDR52/DDR50 to other SDR or HS > > modes like incase of mmc_retune where it switches from HS400 to HS > > DDR and then from HS DDR to HS mode and then to HS200. > > > > This patch fixes the ddr_signaling to set properly for non DDR modes. > > > > Tested-by: Jon Hunter <jonathanh@xxxxxxxxxx> > > Acked-by: Adrian Hunter <adrian.hunter@xxxxxxxxx> > > Signed-off-by: Sowjanya Komatineni <skomatineni@xxxxxxxxxx> > > Is this a fix and/or shall I tag it for stable? > > The series looks good to me, however I am awaiting two more acks from Adrian on patch 2 and patch3. > > Kind regards > Uffe > > Thanks Uffe. Yes this is applicable for stable. Just sent updated patch series V4 with minor fix for avoiding build error warning. Didn’t see earlier and found missing -Werror flag during build. So fixed in V4. > > --- > > drivers/mmc/host/sdhci-tegra.c | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/drivers/mmc/host/sdhci-tegra.c > > b/drivers/mmc/host/sdhci-tegra.c index 32e62904c0d3..46086dd43bfb > > 100644 > > --- a/drivers/mmc/host/sdhci-tegra.c > > +++ b/drivers/mmc/host/sdhci-tegra.c > > @@ -779,6 +779,7 @@ static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host, > > bool set_dqs_trim = false; > > bool do_hs400_dll_cal = false; > > > > + tegra_host->ddr_signaling = false; > > switch (timing) { > > case MMC_TIMING_UHS_SDR50: > > case MMC_TIMING_UHS_SDR104: > > -- > > 2.7.4 > >