Re: [PATCH V2] mmc: sdhci-esdhc-imx: clear the HALT bit when enable CQE

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On 26/02/19 5:23 AM, BOUGH CHEN wrote:
> After system suspend, CQE is in cqhci_off state, which set the HALT bit, make
> CQE in HALT state. If the SoC do not power down the USDHC module, then when
> system resume back, this bit keep the same, still set. Though there is a
> sdhci reset during sdhci_resume_host(), but this reset do not impact the
> CQE part, so need to clear this bit when enable CQE, otherwise CQE will
> stuck in the first CMDQ request after system resume back.
> 
> Find this issue on NXP i.MX845s-mek board
> 
> [  105.919862] mmc2: cqhci: timeout for tag 6
> [  105.923965] mmc2: cqhci: ============ CQHCI REGISTER DUMP ===========
> [  105.930407] mmc2: cqhci: Caps:      0x0000310a | Version:  0x00000510
> [  105.936847] mmc2: cqhci: Config:    0x00001001 | Control:  0x00000001
> [  105.943286] mmc2: cqhci: Int stat:  0x00000000 | Int enab: 0x00000006
> [  105.949725] mmc2: cqhci: Int sig:   0x00000006 | Int Coal: 0x00000000
> [  105.956164] mmc2: cqhci: TDL base:  0x7809b000 | TDL up32: 0x00000000
> [  105.962604] mmc2: cqhci: Doorbell:  0x00000040 | TCN:      0x00000000
> [  105.969043] mmc2: cqhci: Dev queue: 0x00000000 | Dev Pend: 0x00000000
> [  105.975483] mmc2: cqhci: Task clr:  0x00000000 | SSC1:     0x00011000
> [  105.981922] mmc2: cqhci: SSC2:      0x00000001 | DCMD rsp: 0x00000000
> [  105.988362] mmc2: cqhci: RED mask:  0xfdf9a080 | TERRI:    0x00000000
> [  105.994801] mmc2: cqhci: Resp idx:  0x00000000 | Resp arg: 0x00000000
> [  106.001240] mmc2: sdhci: ============ SDHCI REGISTER DUMP ===========
> [  106.007680] mmc2: sdhci: Sys addr:  0xb2b37800 | Version:  0x00000002
> [  106.014120] mmc2: sdhci: Blk size:  0x00000200 | Blk cnt:  0x00000001
> [  106.020560] mmc2: sdhci: Argument:  0x00010000 | Trn mode: 0x00000013
> [  106.026999] mmc2: sdhci: Present:   0x01f88008 | Host ctl: 0x00000030
> [  106.033439] mmc2: sdhci: Power:     0x00000002 | Blk gap:  0x00000080
> [  106.039878] mmc2: sdhci: Wake-up:   0x00000008 | Clock:    0x0000000f
> [  106.046318] mmc2: sdhci: Timeout:   0x0000008f | Int stat: 0x00000000
> [  106.052757] mmc2: sdhci: Int enab:  0x107f4000 | Sig enab: 0x107f4000
> [  106.059196] mmc2: sdhci: AC12 err:  0x00000000 | Slot int: 0x00000502
> [  106.065635] mmc2: sdhci: Caps:      0x07eb0000 | Caps_1:   0x8000b407
> [  106.072075] mmc2: sdhci: Cmd:       0x00000d1a | Max curr: 0x00ffffff
> [  106.078514] mmc2: sdhci: Resp[0]:   0x00000900 | Resp[1]:  0x31360181
> [  106.084954] mmc2: sdhci: Resp[2]:   0x44473430 | Resp[3]:  0x00450100
> [  106.091392] mmc2: sdhci: Host ctl2: 0x00000008
> [  106.095836] mmc2: sdhci: ADMA Err:  0x00000000 | ADMA Ptr: 0x7804b208
> [  106.102274] mmc2: sdhci: ============================================
> [  106.108785] mmc2: running CQE recovery
> 
> Signed-off-by: Haibo Chen <haibo.chen@xxxxxxx>

Minor comment below, nevertheless:

Acked-by: Adrian Hunter <adrian.hunter@xxxxxxxxx>

> 
> ---
> Changes for V2
> - move the clear HALT behavior from common code __cqhci_enable to platform
> specific function esdhc_cqe_enable
> ---
>  drivers/mmc/host/sdhci-esdhc-imx.c | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
> index c7215f5321d7..e2523beb495d 100644
> --- a/drivers/mmc/host/sdhci-esdhc-imx.c
> +++ b/drivers/mmc/host/sdhci-esdhc-imx.c
> @@ -1245,6 +1245,7 @@ static void sdhci_esdhc_imx_hwinit(struct sdhci_host *host)
>  static void esdhc_cqe_enable(struct mmc_host *mmc)
>  {
>  	struct sdhci_host *host = mmc_priv(mmc);
> +	struct cqhci_host *cq_host = mmc->cqe_private;
>  	u32 reg;
>  	u16 mode;
>  	int count = 10;
> @@ -1277,6 +1278,18 @@ static void esdhc_cqe_enable(struct mmc_host *mmc)
>  		mode |= SDHCI_TRNS_BLK_CNT_EN;
>  	sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
>  
> +	/*
> +	 * Though Runtime resume reset the entire host controller,
> +	 * but do not impact the CQHCI side, need to clear the
> +	 * HALT bit and clear all tasks, avoid CQHCI stuck in the

This is not clearing all tasks, so this comment is misleading.

> +	 * first request when system resume back.
> +	 */
> +	cqhci_writel(cq_host, 0, CQHCI_CTL);
> +	if (cqhci_readl(cq_host, CQHCI_CTL) && CQHCI_HALT)
> +		dev_err(mmc_dev(host->mmc),
> +			"failed to exit halt state when enable CQE\n");
> +
> +
>  	sdhci_cqe_enable(mmc);
>  }
>  
> 




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