On Fri, 21 Dec 2018 at 10:20, BOUGH CHEN <haibo.chen@xxxxxxx> wrote:
>
> DDR50 tuning is optinally defined in sd 3.0 spec. And i.MX
> uSDHC internally already uses a fixed optimized timing for
> DDR50, normally does not require tuning for DDR50 mode.
>
> This patch specify a new execute_tuning function for i.MX
> uSDHC, do not impact i.MX eSDHC.
>
> Signed-off-by: Haibo Chen <haibo.chen@xxxxxxx>
Applied for next, thanks!
Kind regards
Uffe
> ---
> drivers/mmc/host/sdhci-esdhc-imx.c | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
> index 75a2484..748ac4e 100644
> --- a/drivers/mmc/host/sdhci-esdhc-imx.c
> +++ b/drivers/mmc/host/sdhci-esdhc-imx.c
> @@ -818,6 +818,20 @@ static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
> SDHCI_HOST_CONTROL);
> }
>
> +static int usdhc_execute_tuning(struct mmc_host *mmc, u32 opcode)
> +{
> + struct sdhci_host *host = mmc_priv(mmc);
> +
> + /*
> + * i.MX uSDHC internally already uses a fixed optimized timing for
> + * DDR50, normally does not require tuning for DDR50 mode.
> + */
> + if (host->timing == MMC_TIMING_UHS_DDR50)
> + return 0;
> +
> + return sdhci_execute_tuning(mmc, opcode);
> +}
> +
> static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val)
> {
> u32 reg;
> @@ -1338,6 +1352,12 @@ static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
> writel(0x0, host->ioaddr + ESDHC_MIX_CTRL);
> writel(0x0, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
> writel(0x0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
> +
> + /*
> + * Link usdhc specific mmc_host_ops execute_tuning function,
> + * to replace the standard one in sdhci_ops.
> + */
> + host->mmc_host_ops.execute_tuning = usdhc_execute_tuning;
> }
>
> if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
> --
> 1.9.1
>
