Hi Loic, On 11/22/18 12:18, Loic Poulain wrote:
The Clock Data Recovery (CDR) circuit allows to automatically adjust the RX sampling-point/phase for high frequency cards (SDR104, HS200...). CDR is automatically enabled during DLL configuration. However, according to the APQ8016 reference manual, this function must be disabled during TX and tuning phase in order to prevent any interferences during tuning challenges and unexpected phase alteration during TX transfers. This patch enables/disables CDR according to the current transfer mode. This fixes sporadic write transfer issues observed with some SDR104 and HS200 cards.
Thanks for the patch! It also fixes similar issue on APQ8096 devices.
Inspired by sdhci-msm downstream patch: https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/432516/ Reported-by: Leonid Segal <leonid.s@xxxxxxxxxxxxx> Reported-by: Manabu Igusa <migusa@xxxxxxxxxxxxxx> Signed-off-by: Loic Poulain <loic.poulain@xxxxxxxxxx>
Acked-by: Georgi Djakov <georgi.djakov@xxxxxxxxxx> BR, Georgi
