Hi Chris, > +/* RZ/A2 does not have the ADRR_MODE bit */ > +#define SDHI_INTERNAL_DMAC_ADRR_MODE_FIXED 2 First, there is a typo: s/ADRR/ADDR/g Also, I think it would make the code much more comprehensible if this macro was named SDHI_INTERNAL_DMAC_ADDR_MODE_BROKEN. Or maybe SDHI_INTERNAL_DMAC_FIXED_ADDR_MODE_BROKEN. Currently, on first read I thought this mode was fixed on this SoC and broken on all the others and was confused. What do you think? Rest looks okay to me! Regards, Wolfram
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