On Thu, Aug 16, 2018 at 04:16:34PM +0900, Masahiro Yamada wrote: > tmio_mmc_set_clock() is full of quirks because different SoC vendors > extended this in different ways. > > The original IP defines the divisor range 1/2 ... 1/512. > > bit 7 is set: 1/512 > bit 6 is set: 1/256 > ... > bit 0 is set: 1/4 > all bits clear: 1/2 > > It is platform-dependent how to achieve the 1/1 clock. > > I guess the TMIO-MFD variant uses the clock selector outside of this IP, > as far as I see tmio_core_mmc_clk_div() in drivers/mfd/tmio_core.c > > I guess bit[7:0]=0xff is Renesas-specific extension. > > Socionext (and Panasonic) uses bit 10 (CLKSEL) for 1/1. Also, newer > versions of UniPhier SoC variants use bit 16 for 1/1024. > > host->clk_update() is only used by the Renesas variants, whereas > host->set_clk_div() is only used by the TMIO-MFD variants. > > To cope with this mess, promote tmio_mmc_set_clock() to a new > platform hook ->set_clock(), and melt the old two hooks into it. > > Signed-off-by: Masahiro Yamada <yamada.masahiro@xxxxxxxxxxxxx> Reviewed-by: Wolfram Sang <wsa+renesas@xxxxxxxxxxxxxxxxxxxx> I like this refactoring, much clearer this way. Thanks.
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