Hi lkp, this patch compile error is due to it is not svnchronized in time that follow the another patch "mmc: sd: Define name for default speed dtr", I consider Adrian hunter's advice, that I will give a new version for this. Thanks Regards, Yinbo -----Original Message----- From: kbuild test robot [mailto:lkp@xxxxxxxxx] Sent: 2018年5月30日 17:04 To: Yinbo Zhu <yinbo.zhu@xxxxxxx> Cc: kbuild-all@xxxxxx; Yinbo Zhu <yinbo.zhu@xxxxxxx>; Y.b. Lu <yangbo.lu@xxxxxxx>; Adrian Hunter <adrian.hunter@xxxxxxxxx>; linux-mmc@xxxxxxxxxxxxxxx; Xiaobo Xie <xiaobo.xie@xxxxxxx> Subject: Re: [PATCH v2] mmc: sdhci-of-esdhc: modify the sd clock in soc_device_match way Hi yinbo.zhu, Thank you for the patch! Yet something to improve: [auto build test ERROR on linus/master] [also build test ERROR on v4.17-rc7 next-20180529] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.com%2F0day-ci%2Flinux%2Fcommits%2FYinbo-Zhu%2Fmmc-sdhci-of-esdhc-modify-the-sd-clock-in-soc_device_match-way%2F20180524-164326&data=02%7C01%7Cyinbo.zhu%40nxp.com%7C10f70ccc11e447b63f1208d5c60c6a60%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C636632682102290618&sdata=rfubgM%2FTqTFqkyVxJCK%2FLhVR%2BB5bmZGTRDCd1LgwE8w%3D&reserved=0 config: arm-allmodconfig (attached as .config) compiler: arm-linux-gnueabi-gcc (Debian 7.2.0-11) 7.2.0 reproduce: wget https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fraw.githubusercontent.com%2Fintel%2Flkp-tests%2Fmaster%2Fsbin%2Fmake.cross&data=02%7C01%7Cyinbo.zhu%40nxp.com%7C10f70ccc11e447b63f1208d5c60c6a60%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C636632682102290618&sdata=MrUHMMy5HWaanczMNS%2BhW1KCezhejmWKbW3XOXodP2o%3D&reserved=0 -O ~/bin/make.cross chmod +x ~/bin/make.cross # save the attached .config to linux build tree make.cross ARCH=arm All errors (new ones prefixed by >>): drivers/mmc/host/sdhci-of-esdhc.c: In function 'esdhc_of_set_clock': >> drivers/mmc/host/sdhci-of-esdhc.c:567:36: error: 'FULL_SPEED_MAX_DTR' undeclared (first use in this function); did you mean 'HIGH_SPEED_MAX_DTR'? clock = esdhc_clock_fixup(clock, FULL_SPEED_MAX_DTR, fixup); ^~~~~~~~~~~~~~~~~~ HIGH_SPEED_MAX_DTR drivers/mmc/host/sdhci-of-esdhc.c:567:36: note: each undeclared identifier is reported only once for each function it appears in vim +567 drivers/mmc/host/sdhci-of-esdhc.c 542 543 static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock) 544 { 545 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 546 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 547 int pre_div = 1; 548 int div = 1; 549 ktime_t timeout; 550 long fixup; 551 u32 temp; 552 553 host->mmc->actual_clock = 0; 554 555 if (clock == 0) { 556 esdhc_clock_enable(host, false); 557 return; 558 } 559 560 /* Workaround to start pre_div at 2 for VNN < VENDOR_V_23 */ 561 if (esdhc->vendor_ver < VENDOR_V_23) 562 pre_div = 2; 563 564 switch (host->mmc->ios.timing) { 565 case MMC_TIMING_LEGACY: 566 fixup = esdhc->clk_fixup->ds; > 567 clock = esdhc_clock_fixup(clock, FULL_SPEED_MAX_DTR, fixup); 568 fixup = esdhc->clk_fixup->mmc_ds; 569 clock = esdhc_clock_fixup(clock, MMC_HIGH_26_MAX_DTR, fixup); 570 break; 571 case MMC_TIMING_SD_HS: 572 fixup = esdhc->clk_fixup->hs; 573 clock = esdhc_clock_fixup(clock, HIGH_SPEED_MAX_DTR, fixup); 574 break; 575 case MMC_TIMING_MMC_HS: 576 fixup = esdhc->clk_fixup->mmc_hs; 577 clock = esdhc_clock_fixup(clock, MMC_HIGH_52_MAX_DTR, fixup); 578 break; 579 case MMC_TIMING_UHS_SDR104: 580 fixup = esdhc->clk_fixup->sdr104; 581 clock = esdhc_clock_fixup(clock, UHS_SDR104_MAX_DTR, fixup); 582 break; 583 case MMC_TIMING_MMC_HS200: 584 fixup = esdhc->clk_fixup->hs200; 585 clock = esdhc_clock_fixup(clock, MMC_HS200_MAX_DTR, fixup); 586 break; 587 default: 588 break; 589 } 590 591 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 592 temp &= ~(ESDHC_CLOCK_SDCLKEN | ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | 593 ESDHC_CLOCK_PEREN | ESDHC_CLOCK_MASK); 594 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 595 596 while (host->max_clk / pre_div / 16 > clock && pre_div < 256) 597 pre_div *= 2; 598 599 while (host->max_clk / pre_div / div > clock && div < 16) 600 div++; 601 602 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", 603 clock, host->max_clk / pre_div / div); 604 host->mmc->actual_clock = host->max_clk / pre_div / div; 605 pre_div >>= 1; 606 div--; 607 608 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 609 temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 610 | (div << ESDHC_DIVIDER_SHIFT) 611 | (pre_div << ESDHC_PREDIV_SHIFT)); 612 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 613 614 /* Wait max 20 ms */ 615 timeout = ktime_add_ms(ktime_get(), 20); 616 while (!(sdhci_readl(host, ESDHC_PRSSTAT) & ESDHC_CLOCK_STABLE)) { 617 if (ktime_after(ktime_get(), timeout)) { 618 pr_err("%s: Internal clock never stabilised.\n", 619 mmc_hostname(host->mmc)); 620 return; 621 } 622 udelay(10); 623 } 624 625 temp |= ESDHC_CLOCK_SDCLKEN; 626 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 627 } 628 --- 0-DAY kernel test infrastructure Open Source Technology Center https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.01.org%2Fpipermail%2Fkbuild-all&data=02%7C01%7Cyinbo.zhu%40nxp.com%7C10f70ccc11e447b63f1208d5c60c6a60%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C636632682102290618&sdata=FBlJ3bdWhYaBSqGq1nn%2BoPTEVXk1MTZfgI3gbk2l05Q%3D&reserved=0 Intel Corporation ?韬{.n?????%??檩??w?{.n???{炳i?)?骅w* jg????????G??⒏ ⒎?:+v???????? ????＂??????
