Hi
On 2017/8/17 15:45, Bough Chen wrote:
-----Original Message-----
From: linux-mmc-owner@xxxxxxxxxxxxxxx [mailto:linux-mmc-
owner@xxxxxxxxxxxxxxx] On Behalf Of Adrian Hunter
Sent: Thursday, August 10, 2017 8:08 PM
To: Ulf Hansson <ulf.hansson@xxxxxxxxxx>
Cc: linux-mmc <linux-mmc@xxxxxxxxxxxxxxx>; Bough Chen
<haibo.chen@xxxxxxx>; Alex Lemberg <alex.lemberg@xxxxxxxxxxx>;
Mateusz Nowak <mateusz.nowak@xxxxxxxxx>; Yuliy Izrailov
<Yuliy.Izrailov@xxxxxxxxxxx>; Jaehoon Chung <jh80.chung@xxxxxxxxxxx>;
Dong Aisheng <dongas86@xxxxxxxxx>; Das Asutosh
<asutoshd@xxxxxxxxxxxxxx>; Zhangfei Gao <zhangfei.gao@xxxxxxxxx>;
Sahitya Tummala <stummala@xxxxxxxxxxxxxx>; Harjani Ritesh
<riteshh@xxxxxxxxxxxxxx>; Venu Byravarasu <vbyravarasu@xxxxxxxxxx>;
Linus Walleij <linus.walleij@xxxxxxxxxx>; Shawn Lin <shawn.lin@xxxxxxxxxxxxxx>
Subject: [PATCH V5 00/13] mmc: Add Command Queue support
Hi
Here is V5 of the hardware command queue patches without the software
command queue patches.
HW CMDQ offers 25% - 50% better random multi-threaded I/O. I see a slight 2%
drop in sequential read speed but no change to sequential write.
Hi Adrian,
I test the performance on the i.MX8. Here in my side, I use 'dd' to test the
sequential read/write speed, see a slight 3% drop for both read and write.
---------------------------------------------
| | read (KB/s)| write (KB/s) |
---------------------------------------------
|CMDQ in HS400ES| 257 | 94.5 |
---------------------------------------------
| HS400ES | 265 | 96.6 |
---------------------------------------------
For random multi-threaded I/O, I use 'fio' to test, the test command:
fio -filename=/mnt/test -direct=1 -iodepth 1 -thread -rw=randread - ioengine=psync -bs=4k -size=2G -numjobs=10 -runtime=60 -group_reporting - name=mytest
I test 5 times, and get the average value.
For CMDQ in HS400ES
----------------------------------------------------
| block size | 4KB | 8KB | 16KB |
----------------------------------------------------
| random read | 26340KB/s | 51844KB/s | 85738KB/s |
----------------------------------------------------
| random write | 12691KB/s | 15879KB/s | 17535KB/s |
----------------------------------------------------
HS400ES without CMDQ
----------------------------------------------------
| block size | 4KB | 8KB | 16KB |
----------------------------------------------------
| random read | 18585KB/s | 35041KB/s | 63880KB/s |
----------------------------------------------------
| random write | 16465KB/s | 19210KB/s | 22672KB/s |
----------------------------------------------------
For random write from the test, I find every test value differ greatly no matter enable CMDQ or not.
From the test, I see CMDQ random read speed increase 34%~48%, but for random write, the speed
drop 17.4% ~ 33%.
When you send software cmdq V5 patch, you give some explanation for the random write. But the
average random write speed also drops a lot, I think it is now a good news, which need attention!
Maybe Shawn Lin can double test this random write performance.
Yes, I also find the performance fluctuates a lot for different
eMMC chips when enabling CMDQ. I will need more data to check that.
Will update it later.
Best Regards
Haibo Chen
Changes since V4:
mmc: core: Add mmc_retune_hold_now()
Add explanation to commit message.
mmc: host: Add CQE interface
Add comments to callback declarations.
mmc: core: Turn off CQE before sending commands
Add explanation to commit message.
mmc: core: Add support for handling CQE requests
Add comments as requested by Ulf.
mmc: core: Remove unused MMC_CAP2_PACKED_CMD
New patch.
mmc: mmc: Enable Command Queuing
Adjust for removal of MMC_CAP2_PACKED_CMD.
Add a comment about Packed Commands.
mmc: mmc: Enable CQE's
Remove un-necessary check for MMC_CAP2_CQE
mmc: block: Use local variables in mmc_blk_data_prep()
New patch.
mmc: block: Prepare CQE data
Adjust due to "mmc: block: Use local variables in
mmc_blk_data_prep()"
Remove priority setting.
Add explanation to commit message.
mmc: cqhci: support for command queue enabled host
Fix transfer descriptor setting in cqhci_set_tran_desc() for 32-bit DMA
Changes since V3:
Adjusted ...blk_end_request...() for new block status codes
Fixed CQHCI transaction descriptor for "no DCMD" case
Changes since V2:
Dropped patches that have been applied.
Re-based
Added "mmc: sdhci-pci: Add CQHCI support for Intel GLK"
Changes since V1:
"Share mmc request array between partitions" is dependent
on changes in "Introduce queue semantics", so added that
and block fixes:
Added "Fix is_waiting_last_req set incorrectly"
Added "Fix cmd error reset failure path"
Added "Use local var for mqrq_cur"
Added "Introduce queue semantics"
Changes since RFC:
Re-based on next.
Added comment about command queue priority.
Added some acks and reviews.
Adrian Hunter (12):
mmc: core: Add mmc_retune_hold_now()
mmc: core: Add members to mmc_request and mmc_data for CQE's
mmc: host: Add CQE interface
mmc: core: Turn off CQE before sending commands
mmc: core: Add support for handling CQE requests
mmc: core: Remove unused MMC_CAP2_PACKED_CMD
mmc: mmc: Enable Command Queuing
mmc: mmc: Enable CQE's
mmc: block: Use local variables in mmc_blk_data_prep()
mmc: block: Prepare CQE data
mmc: block: Add CQE support
mmc: sdhci-pci: Add CQHCI support for Intel GLK
Venkat Gopalakrishnan (1):
mmc: cqhci: support for command queue enabled host
drivers/mmc/core/block.c | 238 +++++++-
drivers/mmc/core/block.h | 7 +
drivers/mmc/core/bus.c | 7 +
drivers/mmc/core/core.c | 178 +++++-
drivers/mmc/core/host.c | 6 +
drivers/mmc/core/host.h | 1 +
drivers/mmc/core/mmc.c | 42 +-
drivers/mmc/core/queue.c | 273 ++++++++-
drivers/mmc/core/queue.h | 42 +-
drivers/mmc/host/Kconfig | 14 +
drivers/mmc/host/Makefile | 1 +
drivers/mmc/host/cqhci.c | 1154
+++++++++++++++++++++++++++++++++++++
drivers/mmc/host/cqhci.h | 240 ++++++++
drivers/mmc/host/sdhci-pci-core.c | 153 ++++-
include/linux/mmc/core.h | 18 +-
include/linux/mmc/host.h | 63 +-
include/trace/events/mmc.h | 36 +-
17 files changed, 2412 insertions(+), 61 deletions(-) create mode 100644
drivers/mmc/host/cqhci.c create mode 100644 drivers/mmc/host/cqhci.h
Regards
Adrian
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