Hi Rob, On Wed, Jan 04, 2017 at 08:07:50AM -0600, Rob Herring wrote: > On Mon, Jan 02, 2017 at 11:03:43PM +0000, Andre Przywara wrote: > > From: Maxime Ripard <maxime.ripard@xxxxxxxxxxxxxxxxxx> > > > > Unlike the A64 user manual reports, the third MMC controller on the > > A64 (and the only one capable of 8-bit HS400 eMMC transfers) has a > > DMA buffer size limit of 8KB (much like the very old Allwinner SoCs). > > This does not affect the other two controllers, so introduce a new > > DT compatible string to let the driver use different settings for that > > particular device. This will also help to enable the high-speed transfer > > modes of that controller later. > > > > Signed-off-by: Maxime Ripard <maxime.ripard@xxxxxxxxxxxxxxxxxx> > > Signed-off-by: Andre Przywara <andre.przywara@xxxxxxx> > > --- > > Documentation/devicetree/bindings/mmc/sunxi-mmc.txt | 1 + > > drivers/mmc/host/sunxi-mmc.c | 7 +++++++ > > 2 files changed, 8 insertions(+) > > Acked-by: Rob Herring <robh@xxxxxxxxxx> Some kind of a digression on this: we have three MMC controllers on this SoC. Like this patch shows, the third one is clearly different, and supports both more modes, a wider bus, and specific quirks. We need a new compatible for this one, everything's perfect. However, the other two are mostly the same, but seems to need different tuning parameters to get more performances out of the controller (but this is unclear yet). How do we usually deal with that? Thanks, Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com
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