On 14/11/16 08:38, Shyam Sundar S K wrote:
>
>
> On 11/11/2016 6:11 PM, Adrian Hunter wrote:
>> On 10/11/16 14:51, Shyam Sundar S K wrote:
>>> This patch adds support for HS200 tuning mode on AMD eMMC-4.5.1
>>>
>>> Reviewed-by: Sen, Pankaj <Pankaj.Sen@xxxxxxx>
>>> Reviewed-by: Shah, Nehal-bakulchandra <Nehal-bakulchandra.Shah@xxxxxxx>
>>> Signed-off-by: S-k, Shyam-sundar <Shyam-sundar.S-k@xxxxxxx>
>>> ---
>>> drivers/mmc/host/sdhci-pci-core.c | 178 +++++++++++++++++++++++++++++++++++++-
>>> 1 file changed, 177 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/mmc/host/sdhci-pci-core.c b/drivers/mmc/host/sdhci-pci-core.c
>>> index 782c8d2..9576f82 100644
>>> --- a/drivers/mmc/host/sdhci-pci-core.c
>>> +++ b/drivers/mmc/host/sdhci-pci-core.c
>>> @@ -817,6 +817,171 @@ enum amd_chipset_gen {
>>> AMD_CHIPSET_UNKNOWN,
>>> };
>>>
>>> +static const struct sdhci_ops amd_sdhci_pci_ops;
>>> +
>>> +struct amd_tuning_descriptor {
>>> + u8 tune_around;
>>> + bool this_tune_ok;
>>> + bool last_tune_ok;
>>> + u8 valid_front;
>>> + u8 valid_window_max;
>>> + u8 tune_low_max;
>>> + u8 tune_low;
>>> + u8 valid_window;
>>> + u8 tune_result;
>>> +};
>>> +
>>> +static int amd_tuning_reset(struct sdhci_host *host)
>>> +{
>>> + unsigned int val;
>>> + unsigned long flags;
>>> +
>>> + spin_lock_irqsave(&host->lock, flags);
>>> +
>>> + val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
>>> + val |= SDHCI_CTRL_PRESET_VAL_ENABLE | SDHCI_CTRL_EXEC_TUNING;
>>> + sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
>>> +
>>> + val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
>>> + val &= ~SDHCI_CTRL_EXEC_TUNING;
>>> + sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
>>> +
>>> + spin_unlock_irqrestore(&host->lock, flags);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static int amd_config_tuning_phase(struct sdhci_host *host, u8 phase)
>>> +{
>>> + struct sdhci_pci_slot *slot = sdhci_priv(host);
>>> + struct pci_dev *pdev = slot->chip->pdev;
>>> + unsigned int val;
>>> + unsigned long flags;
>>> +
>>> + spin_lock_irqsave(&host->lock, flags);
>>> +
>>> + pci_read_config_dword(pdev, 0xb8, &val);
>>> + val &= ~0x1f;
>>> + val |= (0x10800 | (phase << 1));
>>> + pci_write_config_dword(pdev, 0xb8, val);
>>> +
>>> + spin_unlock_irqrestore(&host->lock, flags);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static int amd_find_good_phase(struct sdhci_host *host)
>>> +{
>>> + struct sdhci_pci_slot *slot = sdhci_priv(host);
>>> + struct pci_dev *pdev = slot->chip->pdev;
>>> + struct amd_tuning_descriptor *td = sdhci_pci_priv(slot);
>>> +
>>> + unsigned int val;
>>> + unsigned long flags;
>>> +
>>> + spin_lock_irqsave(&host->lock, flags);
>>> +
>>> + if (td->this_tune_ok)
>>> + td->valid_front += 1;
>>> + if ((!td->this_tune_ok && td->last_tune_ok) ||
>>> + (td->tune_around == 11)) {
>>> + if (td->valid_window > td->valid_window_max) {
>>> + td->valid_window_max = td->valid_window;
>>> + td->tune_low_max = td->tune_low;
>>> + }
>>> + }
>>> + if (td->this_tune_ok && (!td->last_tune_ok))
>>> + td->tune_low = td->tune_around;
>>> + if (!td->this_tune_ok && td->last_tune_ok)
>>> + td->valid_window = 0;
>>> + else if (td->this_tune_ok)
>>> + td->valid_window += 1;
>>> +
>>> + td->last_tune_ok = td->this_tune_ok;
>>> +
>>> + if (td->tune_around == 11) {
>>> + if ((td->valid_front + td->valid_window) >
>>> + td->valid_window_max) {
>>> + if (td->valid_front > td->valid_window)
>>> + td->tune_result = ((td->valid_front -
>>> + td->valid_window) >> 1);
>>> + else
>>> + td->tune_result = td->tune_low +
>>> + ((td->valid_window + td->valid_front) >> 1);
>>> + } else {
>>> + td->tune_result = td->tune_low_max +
>>> + (td->valid_window_max >> 1);
>>> + }
>>> +
>>> + if (td->tune_result > 0x0b)
>>> + td->tune_result = 0x0b;
>>> +
>>> + pci_read_config_dword(pdev, 0xb8, &val);
>>> + val &= ~0x1f;
>>> + val |= (0x10800 | (td->tune_result << 1));
>>> + pci_write_config_dword(pdev, 0xb8, val);
>>> + }
>>> +
>>> + spin_unlock_irqrestore(&host->lock, flags);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static int amd_enable_manual_tuning(struct sdhci_pci_slot *slot)
>>> +{
>>> + struct pci_dev *pdev = slot->chip->pdev;
>>> + unsigned int val;
>>> +
>>> + pci_read_config_dword(pdev, 0xd0, &val);
>>> + val &= 0xffffffcf;
>>> + val |= 0x30;
>>> + pci_write_config_dword(pdev, 0xd0, val);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static int amd_execute_tuning(struct sdhci_host *host, u32 opcode)
>>> +{
>>> + struct sdhci_pci_slot *slot = sdhci_priv(host);
>>> + struct amd_tuning_descriptor *td = sdhci_pci_priv(slot);
>>> + u8 ctrl;
>>> +
>>> + amd_tuning_reset(host);
>>> + memset(td, 0, sizeof(struct amd_tuning_descriptor));
>>
>> I didn't notice last time that you are always clearing all the values in the
>> tuning descriptor, so it doesn't need to be kept between calls to
>> amd_execute_tuning(). So it should be a local variable that you pass to the
>> functions that need it. Then you don't need the patch I sent at all.
>>
>> Does that make sense?
>>
>
> Hi Adrian,
>
> Thanks for pointing this out. Your patch will help, so will remove the memset()
> and redo the submission. Is this OK ?
Sure
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