On Mon, Sep 12, 2016 at 10:15:06AM -0400, Chris Brandt wrote: > For the r7s72100 SOC, the DATA_PORT register was changed to 32-bits wide. > Therefore a new flag has been created that will allow 32-bit reads/writes > to the DATA_PORT register instead of 16-bit (because 16-bits accesses are > not supported). > > Signed-off-by: Chris Brandt <chris.brandt@xxxxxxxxxxx> > --- > v3: > * changed loops to memcpy > v2: > * changed 'data * 0xFF' to 'data & 0xFF' > * added 'const' for sd_ctrl_write32_rep Sadly, I don't have SDHI documentation for this SoC. * Does it have a version register (CTL_VERSION)? If so, what does it say? * Does it have SD_BUF0 width setting (named either EXT_ACC or HOST_MODE, so far always comes after the version register)? If so, what is its layout? Unrelated to this patch but nice to know: * Does it support DMA? Is it compatible to the current implementation? That being asked, R-Car SoCs can have SDBUF0 32-bit wide as well (Gen3 even 64-bit). So far, this is only used for DMA, though. Thanks, Wolfram > + /* if count was multiple of 4 */ > + if (!(count & 0x3)) > + return; > + buf8 = (u8 *)(buf + (count >> 2)); > + count %= 4; To skip the same operation done on 'count' twice, maybe? buf8 = (u8 *)(buf + (count >> 2)); count &= 3; if (!count) return;
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