On 1 September 2016 at 13:46, Thierry Reding <thierry.reding@xxxxxxxxx> wrote:
> From: Thierry Reding <treding@xxxxxxxxxx>
>
> According to the TRM, the SD/MMC controller on Tegra124 supports 34-bit
> addressing, but testing shows that this doesn't work. On a device which
> has more than 2 GiB of RAM and LPAE enabled, buffer allocations can use
> addresses above the 32-bit boundary.
>
> One way to work around this would be to enable IOMMU physical to virtual
> address translations for the SD/MMC controllers, but that's not easy to
> implement without breaking existing use-cases. It's also not obvious why
> 34-bit addressing doesn't work as advertised. In order to fix this for
> existing users, add the SDHCI_QUIRK2_BROKEN_64_BIT_DMA quirk for now.
>
> Reported-by: Paul Kocialkowski <contact@xxxxxxxx>
> Acked-by: Stephen Warren <swarren@xxxxxxxxxx>
> Acked-by: Arnd Bergmann <arnd@xxxxxxxx>
> Acked-by: Adrian Hunter <adrian.hunter@xxxxxxxxx>
> Signed-off-by: Thierry Reding <treding@xxxxxxxxxx>
Thanks, applied for next!
Kind regards
Uffe
> ---
> Changes in v2:
> - add comment with rationale for the quirk
> - add various Acked-bys
>
> drivers/mmc/host/sdhci-tegra.c | 27 ++++++++++++++++++++++++++-
> 1 file changed, 26 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
> index 1e93dc4e303e..20b6ff5b4af1 100644
> --- a/drivers/mmc/host/sdhci-tegra.c
> +++ b/drivers/mmc/host/sdhci-tegra.c
> @@ -391,6 +391,31 @@ static const struct sdhci_tegra_soc_data soc_data_tegra114 = {
> .pdata = &sdhci_tegra114_pdata,
> };
>
> +static const struct sdhci_pltfm_data sdhci_tegra124_pdata = {
> + .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
> + SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
> + SDHCI_QUIRK_SINGLE_POWER_WRITE |
> + SDHCI_QUIRK_NO_HISPD_BIT |
> + SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
> + SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
> + .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
> + /*
> + * The TRM states that the SD/MMC controller found on
> + * Tegra124 can address 34 bits (the maximum supported by
> + * the Tegra memory controller), but tests show that DMA
> + * to or from above 4 GiB doesn't work. This is possibly
> + * caused by missing programming, though it's not obvious
> + * what sequence is required. Mark 64-bit DMA broken for
> + * now to fix this for existing users (e.g. Nyan boards).
> + */
> + SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
> + .ops = &tegra114_sdhci_ops,
> +};
> +
> +static const struct sdhci_tegra_soc_data soc_data_tegra124 = {
> + .pdata = &sdhci_tegra124_pdata,
> +};
> +
> static const struct sdhci_pltfm_data sdhci_tegra210_pdata = {
> .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
> SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
> @@ -408,7 +433,7 @@ static const struct sdhci_tegra_soc_data soc_data_tegra210 = {
>
> static const struct of_device_id sdhci_tegra_dt_match[] = {
> { .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 },
> - { .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra114 },
> + { .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra124 },
> { .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 },
> { .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 },
> { .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 },
> --
> 2.9.3
>
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