Maxime On Wed, Jul 20, 2016 at 08:28:47PM +0200, Jean-Francois Moine wrote: > The rate of the PLL-PERIPH clock is usually set to 1.2GHz in the A83T. Uh? The datasheet says to set it to 600MHz. > This patch sets the phase delays of the output and sample clocks > accordingly. > > Signed-off-by: Jean-Francois Moine <moinejf@xxxxxxx> > --- > Note: The impacted phase delays are only for 50MHz. > The phase delays are not used in 50MHz 8 bits DDR (new timing mode). Actually, they seem to be, in the new timing mode register. Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com
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