On Tue, Jul 5, 2016 at 4:29 PM, Maxime Ripard <maxime.ripard@xxxxxxxxxxxxxxxxxx> wrote: > On Sun, Jul 03, 2016 at 05:20:43PM +0200, Hans de Goede wrote: >> Hi Chen-Yu, >> >> While working on some dts cleanups I tested >> the latest sunxi-next kernel code on my A13 >> Utoo P66 tablet and the emmc no longer works. >> >> The kernel tries to enable DDR52 mode on it, >> since it apparently can do that and after that >> the kernel can no longer talk to it. >> >> Removing MMC_CAP_1_8V_DDR from sunxi-mmc.c >> fixes this. >> >> Part of the problem likely is that it seems >> that the mmc clock on sun4i / sun5i do >> not have sample / output phase clks. >> >> It does not matter what one writes to >> 0x1c20088 / 0x1c20090, bits 8-10 and >> 20-22 are always 0. >> >> I've observed this on both sun4i and sun5i, >> and the sun4i / sun5i datasheets >> also do not mention the phase bits >> for register 0x1c20088 / 0x1c20090. >> >> As such I'm thinking that the best way to fix >> this is: >> >> 1) In sunxi-mmc.c make the sample clocks >> optional; and if not present then do not >> set MMC_CAP_1_8V_DDR (and do not try to >> set sample clks) >> >> 2) Remove the sample clks from the base >> sun4i / sun5i dtsi files > > That looks like the right approach to me. Ack. ChenYu -- To unsubscribe from this list: send the line "unsubscribe linux-mmc" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
