Hello, I had a few doubts regarding 64 bit \ 32 bit \ 8 bit aligned transfers in SDHCI. I am guessing that the alignment is determined by the DMA start address being on 64 (or 32) bit boundary. I am having a SDMA capable SD Host Controller, to verify this I triggered a single block 256 bytes CMD53 write to SDIO device. I read the SDHCI_DMA_ADDRESS register value as 0xb8034a18 before triggering the command and after end of the transfer. What is the default alignment used for DMA transfers, is it 64-bit? But the above mentioned value(0xb8034a18) is neither 64-bit nor 32-bit. Does reading the SDHCI_DMA_ADDRESS register at the end of a transfer indicates the address of the last byte transferred? If so why the value is not changed before and end of the transfer? Any clarifications are welcome. Thanks for your time. -- Thanks, Sekhar -- To unsubscribe from this list: send the line "unsubscribe linux-mmc" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
