On Wed, Nov 18, 2015 at 2:38 PM, Arnd Bergmann <arnd@xxxxxxxx> wrote: > On Wednesday 18 November 2015 11:35:27 Andy Shevchenko wrote: >> On Fri, Nov 13, 2015 at 11:35 AM, Arnd Bergmann <arnd@xxxxxxxx> wrote: >> > On Friday 13 November 2015 03:10:13 Andy Shevchenko wrote: >> >> On Thu, Nov 12, 2015 at 4:14 PM, Arnd Bergmann <arnd@xxxxxxxx> wrote: [] >> >> If dst_addr is dma_addr_t wouldn't be a problem when >> >> resource_size_t is defined as 64-bit address, and dma_addr_t as 32-bit? >> >> >> >> Btw, for me casting to dma_addr_t looks sane. >> > >> > The background here is that the address comes from a resource_size_t >> > that describes the MMIO register area as seen from the CPU, and that >> > is normally a phys_addr_t (resource_size_t is defined as being long >> > enough to store a phys_addr_t or various other things depending on >> > resource->flags). >> > >> > dma_addr_t strictly speaking refers to a RAM location as seen by a >> > DMA master, and that only comes out of dma_map_*() or >> > dma_alloc_coherent(). >> > >> > The DMA engine wants something else here, which is an MMIO register >> > address as seen by a DMA master, and we don't have a separate typedef >> > for that. Almost universally all of resource_size_t, phys_addr_t and >> > dma_addr_t are the same type, and if we ever get a platform that >> > wants something other than a phys_addr_t to put into cfg.dst_addr, >> > we are in deep trouble. >> >> DMA operates with address space covered by dma_addr_t, if you use >> phys_addr_t you may get address out of DMA boundaries. This is should >> be done in hardware / firmware / platform representation. >> So, I don't see any reason not to use dma_addr_t here. > > As I said above, this isn't really the same as DMA: all normal > dma_addr_t are returned from dma_alloc_* or dma_map_*, point > to RAM and might go trhough an IOMMU, all of which is not true > here, hence the patch to change the type to phys_addr_t. > > You really can't get out of bounds because the data comes from a > phys_addr_t and refers to a fixed location in hardware. If a > platform has registers higher than a 32-bit address, its phys_addr_t > must be 64-bit, but its dma_addr_t not necessarily so (even though > the two are the same almost always in practice). I understand most of the things here, what I don't is how a platform is supposed to work if you have the following: a) HW, that uses register space let's say higher than 32-bit; b) DMA engine, which should provide a DMA capability for above HW block; c) dma_addr_t which does not cover the HW register space. For me it clearly looks like a platform (HW / SW) configuration issue. In case of bounce buffers I can't understand how it helps there. -- With Best Regards, Andy Shevchenko -- To unsubscribe from this list: send the line "unsubscribe linux-mmc" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
