On Fri, 2015-08-07 at 10:56 +0800, Yangbo Lu wrote:
> For eSDHC(version < 2.3), the pre divider only could divide base clock
> by 2 at least. Add workaround for this to avoid unexpected issue.
This works for me, I get my 50 MHz bus :)
I would rather se you used the proper register than that SDHCI_SLOT_INT_STATUS hack.
I replaced:
temp = in_be32(host->ioaddr + SDHCI_SLOT_INT_STATUS);
with
temp = esdhc_readw(host, SDHCI_HOST_VERSION);
which yields the same working result for me.
With that change:
Acked-by: Joakim Tjernlund <Joakim.Tjernlund@xxxxxxxxxxxx>
> Signed-off-by: Yangbo Lu <yangbo.lu@xxxxxxxxxxxxx>
> ---
> drivers/mmc/host/sdhci-of-esdhc.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/mmc/host/sdhci-of-esdhc.c b/drivers/mmc/host/sdhci-of-esdhc.c
> index 797be75..46edf2c 100644
> --- a/drivers/mmc/host/sdhci-of-esdhc.c
> +++ b/drivers/mmc/host/sdhci-of-esdhc.c
> @@ -208,6 +208,12 @@ static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock)
> if (clock == 0)
> return;
>
> + /* Workaround to start pre_div at 2 for VNN < VENDOR_V_23 */
> + temp = in_be32(host->ioaddr + SDHCI_SLOT_INT_STATUS);
> + temp = (temp & SDHCI_VENDOR_VER_MASK) >> SDHCI_VENDOR_VER_SHIFT;
> + if (temp < VENDOR_V_23)
> + pre_div = 2;
> +
> /* Workaround to reduce the clock frequency for p1010 esdhc */
> if (of_find_compatible_node(NULL, NULL, "fsl,p1010-esdhc")) {
> if (clock > 20000000)
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