Re: [PATCH 0/2] adds quirk SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN

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On 9 June 2015 at 09:31, Suneel Garapati <suneel.garapati@xxxxxxxxxx> wrote:
> This quirk will support controllers whose clock divider zero is broken
> and if the calculation results to zero, forcing the divider to next value.
> This is tested on zynq ep108 and enables support for UHS cards where formatting
> cards fail. Added few quirks to arasan platform driver as the base clock reported in
> registers is broken and preset values are broken too and tested on zynq ep108
> platform. max-frequency devicetree parameter is alternative to get upper limit .
>
> Suneel Garapati (2):
>   drivers: mmc: add quirk SDHCI_QUIRK_CLOCK_DIV_ZERO_BROKEN
>   drivers: mmc: add quirks for broken clock base
>
>  drivers/mmc/host/sdhci-of-arasan.c | 3 +++
>  drivers/mmc/host/sdhci.c           | 4 ++++
>  drivers/mmc/host/sdhci.h           | 2 ++
>  3 files changed, 9 insertions(+)
>
> --
> 2.1.2

Thanks, applied!

Do note that both patches had checkpatch errors, which complained
about the patch format.
I decided to fix them, but next time please make sure to run checkpatch.

Also, I changed the prefix of patch1 to "mmc: sdhci: and for patch 2
to "mmc: sdhci-of-arasan".

Kind regards
Uffe
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