Hi Geert
Thank you for your feedback
> > +/*
> > + * difference for each SoC
> > + */
> > +struct sh_mmcif_ver {
> > + u32 clkdiv_map; /* see CE_CLK_CTRL::CLKDIV */
> > + unsigned int pf_min; /* parent frequency min */
>
> I don't think you need an explicit lower limit: clk_round_rate() will
> never return a frequency that's lower than the parent clock's lower limit.
Indeed... Good catch
> > +static const struct sh_mmcif_ver sh_mmcif_gen2 = {
> > + .clkdiv_map = 0x3ff,
> > + .pf_min = 12187500,
> > + .pf_max = 97500000,
>
> By any chance, does setting "max-frequency = <97500000>" from the standard
> MMC DT bindings have the same effect?
I'm still not understanding about this.
If we can specify SoC (via compatible), the clock frequency limitation
can be specified in same time.
Why do we need to have flexibility for it ?
What is yuur "any chance" mean ?
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