Dinh, On Fri, Apr 10, 2015 at 11:08 AM, Dinh Nguyen <dinh.linux@xxxxxxxxx> wrote: > > > On 4/10/15 10:15 AM, Doug Anderson wrote: >> Dinh, >> >> On Fri, Apr 10, 2015 at 6:56 AM, <dinguyen@xxxxxxxxxxxxxxxxxxxxx> wrote: >>> From: Dinh Nguyen <dinguyen@xxxxxxxxxxxxxxxxxxxxx> >>> >>> The ciu_clk(Card Interface Unit Clock) on the SoCFPGA platform has a fixed >>> divider of 4. Add the fixed clock divide code in the platform's clock >>> setup code. >> >> It might actually be better to do this a different way for SoCFPGA. I >> sorta wish we had done it differently for Rockchip as well, but at >> this point you end up with the complexity of changing device tree >> bindings in conjunction with code and it gets ugly. > > Yes, I started going down this path and realized that. > >> >> Specifically, you've probably got the following clocks: >> >> SD_prediv = 400MHz >> -> SD postdiv = 100MHz >> -> SD sample = 100MHz, shifted >> -> SD drive = 100MHz, shifted >> >> Right now you're specifying "SD_prediv" as the SD card clock. If you >> instead expose "SD postdiv" as a new clock (from your clock driver) >> that is "SD prediv" divided by 4 then you'll magically get all the >> behavior that you want with no modifications to dw_mmc. Just make >> sure that "SD postdiv" passes on rate changes to its parent (that's >> just a flag in the common clock framework). >> > > That's a great idea, thanks for pointing that out. > >> >> At some point in time you'll also want to expose the sample and drive >> clocks once you get UHS modes working. Alexandru posted some patches >> for this a while ago to support tuning in dw_mmc using just drive and >> sample clocks, but the patch still needed some more work. Either he >> or I will probably pick it up again soon. > > I think I have already done this by representing the sdmmc_clk with a > "clk-phase" property for this clock. I think there needs to be a separate sample and drive clock at least, since they can have different phases, right? I haven't looked, but if that's what you have then you're all set! :) Above I was suggesting a 3rd clock instead of arbitrarily using either the sample/drive clock as the main clock for dw_mmc. -Doug -- To unsubscribe from this list: send the line "unsubscribe linux-mmc" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
