[PATCH RESEND 5/7] mmc: host: dw_mmc make IO accessors endian agnostic

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The dw_mmc driver does not use endian agnostic IO accessors, so fix
the use of __raw reads and writes to be the relaxed versions.

This fixes the dw_mmc driver initialisation on Altera socfpga in big endian.

Signed-off-by: Ben Dooks <ben.dooks@xxxxxxxxxxxxxxx>
--
CC: Linux MMC <linux-mmc@xxxxxxxxxxxxxxx>
CC: Linux ARM Kernel <linux-arm-kernel@xxxxxxxxxxxxxxxxxxx>
CC: Dinh Nguyen <dinguyen@xxxxxxxxxxxxxxxxxxxxx>
CC: Chris Ball <chris@xxxxxxxxxx>
CC: Ulf Hansson <ulf.hansson@xxxxxxxxxx>
CC: Jaehoon Chung <jh80.chung@xxxxxxxxxxx>
CC: Seungwon Jeon <tgih.jun@xxxxxxxxxxx>
---
 drivers/mmc/host/dw_mmc.h | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h
index 18c4afe..46efdc5 100644
--- a/drivers/mmc/host/dw_mmc.h
+++ b/drivers/mmc/host/dw_mmc.h
@@ -171,22 +171,22 @@
 
 /* Register access macros */
 #define mci_readl(dev, reg)			\
-	__raw_readl((dev)->regs + SDMMC_##reg)
+	readl_relaxed((dev)->regs + SDMMC_##reg)
 #define mci_writel(dev, reg, value)			\
-	__raw_writel((value), (dev)->regs + SDMMC_##reg)
+	writel_relaxed((value), (dev)->regs + SDMMC_##reg)
 
 /* 16-bit FIFO access macros */
 #define mci_readw(dev, reg)			\
-	__raw_readw((dev)->regs + SDMMC_##reg)
+	readw_relaxed((dev)->regs + SDMMC_##reg)
 #define mci_writew(dev, reg, value)			\
-	__raw_writew((value), (dev)->regs + SDMMC_##reg)
+	writew_relaxed((value), (dev)->regs + SDMMC_##reg)
 
 /* 64-bit FIFO access macros */
 #ifdef readq
 #define mci_readq(dev, reg)			\
-	__raw_readq((dev)->regs + SDMMC_##reg)
+	readq_relaxed((dev)->regs + SDMMC_##reg)
 #define mci_writeq(dev, reg, value)			\
-	__raw_writeq((value), (dev)->regs + SDMMC_##reg)
+	writeq_relaxed((value), (dev)->regs + SDMMC_##reg)
 #else
 /*
  * Dummy readq implementation for architectures that don't define it.
-- 
2.1.4

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