On 5 November 2014 07:09, Vincent Wan <vincent.wan@xxxxxxx> wrote:
> SDHC controller in AMD chipsets require SDHC transfer mode
> register to be cleared for commands without data. The issue was
> uncovered during testing eMMC cards on KB/ML based platforms
>
> Signed-off-by: Vincent Wan <vincent.wan@xxxxxxx>
> Signed-off-by: Wan Zongshun <mcuos.com@xxxxxxxxx>
> Signed-off-by: Arindam Nath <arindam.nath@xxxxxxx>
> Tested-by: Vikram B <vikram.b@xxxxxxx>
> Tested-by: Raghavendra Swamy <raghavendra.swamy@xxxxxxx>
Thanks! Applied for next.
Kind regards
Uffe
> ---
> drivers/mmc/host/sdhci.c | 9 +++++++--
> include/linux/mmc/sdhci.h | 2 ++
> 2 files changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
> index f895ab0..a743d52 100644
> --- a/drivers/mmc/host/sdhci.c
> +++ b/drivers/mmc/host/sdhci.c
> @@ -915,10 +915,15 @@ static void sdhci_set_transfer_mode(struct sdhci_host *host,
> struct mmc_data *data = cmd->data;
>
> if (data == NULL) {
> + if (host->quirks2 &
> + SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
> + sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
> + } else {
> /* clear Auto CMD settings for no data CMDs */
> - mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
> - sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
> + mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
> + sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
> SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
> + }
> return;
> }
>
> diff --git a/include/linux/mmc/sdhci.h b/include/linux/mmc/sdhci.h
> index 931ac5e..ae7f357 100644
> --- a/include/linux/mmc/sdhci.h
> +++ b/include/linux/mmc/sdhci.h
> @@ -102,6 +102,8 @@ struct sdhci_host {
> #define SDHCI_QUIRK2_STOP_WITH_TC (1<<8)
> /* Controller does not support 64-bit DMA */
> #define SDHCI_QUIRK2_BROKEN_64_BIT_DMA (1<<9)
> +/* need clear transfer mode register before send cmd */
> +#define SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD (1<<10)
>
> int irq; /* Device IRQ */
> void __iomem *ioaddr; /* Mapped address */
> --
> 1.8.1.2
>
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