On 16 January 2014 11:50, Ulf Hansson <ulf.hansson@xxxxxxxxxx> wrote:
> On 15 January 2014 15:10, Seungwon Jeon <tgih.jun@xxxxxxxxxxx> wrote:
>> This change distinguishes DDR timing mode of current
>> mixed usage to clarify device type.
>>
>> Signed-off-by: Seungwon Jeon <tgih.jun@xxxxxxxxxxx>
>
> Acked-by: Ulf Hansson <ulf.hansson@xxxxxxxxxx>
>
>> ---
>> drivers/mmc/core/debugfs.c | 3 +++
>> drivers/mmc/core/mmc.c | 2 +-
>> include/linux/mmc/host.h | 3 ++-
>> 3 files changed, 6 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/mmc/core/debugfs.c b/drivers/mmc/core/debugfs.c
>> index 54829c0..509229b 100644
>> --- a/drivers/mmc/core/debugfs.c
>> +++ b/drivers/mmc/core/debugfs.c
>> @@ -135,6 +135,9 @@ static int mmc_ios_show(struct seq_file *s, void *data)
>> case MMC_TIMING_UHS_DDR50:
>> str = "sd uhs DDR50";
>> break;
>> + case MMC_TIMING_MMC_DDR52:
>> + str = "mmc DDR52";
Just a minor thought. In the eMMC spec there are no such thing as
DDR52 mode. Only DDR is mentioned, should we maybe change to
"MMC_TIMING_MMC_DDR" to better reflect the spec?
Kind regards
Ulf Hansson
>> + break;
>> case MMC_TIMING_MMC_HS200:
>> str = "mmc high-speed SDR200";
>> break;
>> diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c
>> index 98e9eb0..6d91ff7 100644
>> --- a/drivers/mmc/core/mmc.c
>> +++ b/drivers/mmc/core/mmc.c
>> @@ -1261,7 +1261,7 @@ static int mmc_init_card(struct mmc_host *host, u32 ocr,
>> goto err;
>> }
>> mmc_card_set_ddr_mode(card);
>> - mmc_set_timing(card->host, MMC_TIMING_UHS_DDR50);
>> + mmc_set_timing(card->host, MMC_TIMING_MMC_DDR52);
>> mmc_set_bus_width(card->host, bus_width);
>> }
>> }
>> diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h
>> index 99f5709..87b1f4f 100644
>> --- a/include/linux/mmc/host.h
>> +++ b/include/linux/mmc/host.h
>> @@ -58,7 +58,8 @@ struct mmc_ios {
>> #define MMC_TIMING_UHS_SDR50 5
>> #define MMC_TIMING_UHS_SDR104 6
>> #define MMC_TIMING_UHS_DDR50 7
>> -#define MMC_TIMING_MMC_HS200 8
>> +#define MMC_TIMING_MMC_DDR52 8
>> +#define MMC_TIMING_MMC_HS200 9
>>
>> #define MMC_SDR_MODE 0
>> #define MMC_1_2V_DDR_MODE 1
>> --
>> 1.7.0.4
>>
>>
--
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