Hi, Am Montag, 9. Dezember 2013, 05:51:06 schrieb dinguyen@xxxxxxxxxx: > From: Dinh Nguyen <dinguyen@xxxxxxxxxx> > > This patch will enable the SDMMC_CMD_USE_HOLD_REG bit when the slot is > operating all timing modes, except for SDR50, DDR50, SDR104, and MMC_HS200. > > According to the Synopsys databook :"To meet the relatively high Input Hold > Time requirement for SDR12, SDR25, and other MMC speed modes, you should > program bit[29]use_hold_Reg of the CMD register to 1'b1;"..."However, for > the higher speed modes of SDR104, SDR50 and DDR50, you can meet the much > smaller Input Hold Time requirement of 0.8ns by bypassing the Hold Register > (Path A in Figure 10-8, programming CMD.use_hold_reg = 1'b0) and then > adding delay elements on the output path as indicated. > > Also, "Never set CMD.use_hold_reg = 1 and cclk_in_drv phase shift to 0 at > the same time. This would add an extra one-cycle delay on the output path, > resulting in incorrect behavior." > > This patch also checks the IHR(Implement Hold Register) in the HCON > register. > > This information is taking from the v2.50a of the Synopsys Designware Cores > Mobile Storage Host Databook. > > Signed-off-by: Dinh Nguyen <dinguyen@xxxxxxxxxx> > Acked-by: Heiko Stuebner <heiko@xxxxxxxxx> > Tested-by: Heiko Stuebner <heiko@xxxxxxxxx> > --- > v3: Read the IHR(Implement Hold Register) in the HCON > v2: Add check for cclk_in_drv phase shift in conjunction with use_hold_reg. just to say it still works with the v3 changes. Interestingly, the rockchip manual does not specify the hcon register at all, but reading it, I get a value of 0x4c534c1 - letting BIT(22) be the required one. Heiko -- To unsubscribe from this list: send the line "unsubscribe linux-mmc" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
