Grant, Thanks for posting! See below... On Tue, Mar 26, 2013 at 3:50 PM, Grant Grundler <grundler@xxxxxxxxxxxx> wrote: > Last year Seungwon Jeon (Samsung) fixed a bug in CLKDIV computation. > But when debugging a related issue (http://crbug.com/221828) I found > the code unreadable. This rewrite simplifies the computation and > explains each step. The fact that you mention a bug here is confusing. I think this patch has nothing to do with fixing that bug and is just a readability patch. Is that correct? Please add to the description if so and maybe remove unrelated comment about the bug. > + /* don't overclock due to resolution of HW */ > + if (div & 1) > + div++; > + > + /* See 6.2.3 CLKDIV in "Mobile Storage Host Databook" > + * Look for dwc_mobile_storage_db.pdf from Synopsys. > + * CLKDIV value 0 means divisor 1, val 1 -> 2, ... You are quoting exynos5250 docs here. This driver is used for more than just exynos and so this could be confusing to users on other platforms. > */ > - div += 1; > - > - div = (host->bus_hz != slot->clock) ? DIV_ROUND_UP(div, 2) : 0; > + div /= 2; It does look like you're re-implementing DIV_ROUND_UP. Maybe replace your "if" test and division with just a DIV_ROUND_UP? -Doug -- To unsubscribe from this list: send the line "unsubscribe linux-mmc" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
