2012/11/19 Kevin Liu <keyuan.liu@xxxxxxxxx>:
> 2012/11/18 Chris Ball <cjb@xxxxxxxxxx>:
>> Hi,
>>
>> On Wed, Oct 17 2012, Kevin Liu wrote:
>>> diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
>>> index c3e786d..522e501 100644
>>> --- a/drivers/mmc/host/sdhci.c
>>> +++ b/drivers/mmc/host/sdhci.c
>>> @@ -1529,8 +1529,15 @@ static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
>>> ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
>>> else if (ios->timing == MMC_TIMING_UHS_SDR104)
>>> ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
>>> - else if (ios->timing == MMC_TIMING_UHS_DDR50)
>>> + else if (ios->timing == MMC_TIMING_UHS_DDR50) {
>>> + struct mmc_card *card;
>>> +
>>> ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
>>> + card = container_of(&(host->mmc),
>>> + struct mmc_card, host);
>>> + if (mmc_card_mmc(card))
>>> + ctrl_2 |= SDHCI_CTRL_VDD_180;
>>> + }
>>> sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
>>> }
>>> if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
>>
>> I'm using DDR50 on an eMMC that's only powered by 3.3V (no 1.8V
>> available) with sdhci-pxav3, so it sounds like I don't want to merge
>> this patch?
>>
> This patch is NEEDED for both 3.3v and 1.8v signaling.
> In the SD host spec for host control 2 register, 1.8v signaling enable
> bit must be set in order for UHS-I mode taking effect. Otherwise, the
> DDR50 mode won't take effect on host even it is selected.
> It's the SD host requirement.
In fact, I don't think 3.3v vccq for emmc can work under DDR50 mode
with SD host.
You must enable 1.8v signaling on host for UHS-I modes, but you set
3.3v for emmc vccq. It's conflictable.
The only way for emmc DDR50 to work is to set 1.8v for vccq although
JEDEC spec said both 1.8v and 3.3v are ok.
Thanks
Kevin
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