Re: [PATCH] mmc: sh-mmcif: properly handle MMC_WRITE_MULTIPLE_BLOCK completion IRQ

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Hi,

On Tue, Sep 18 2012, Tetsuyuki Kobayashi wrote:
> (2012/09/19 8:10), Guennadi Liakhovetski wrote:
>> Upon completion of a MMC_WRITE_MULTIPLE_BLOCK command MMCIF issues an IRQ
>> with the DTRANE bit set and often with one or several of CMD12 bits set.
>> If those interrupts are not acknowledged, an additional interrupt can be
>> produced and will be delivered later, possibly, when the transaction has
>> already been completed. To prevent this from happening, CMD12 completion
>> interrupt sources have to be cleared too upon reception of an DTRANE IRQ.
>>
>> Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@xxxxxx>
>> ---
>>
>> Tested on kzm9g and mackerel. Kobayashi-san, this fixes spurious
>> interrupts, that you are observing.
>
> I verified on kzm9g.
> This works with
> [PATCH] mmc: sh-mmcif: avoid Oops on spurious interrupts
>
> Tested-by: Tetsuyuki Kobayashi <koba@xxxxxxxxxxx>

Thanks, pushed to mmc-next for 3.7.

- Chris.
-- 
Chris Ball   <cjb@xxxxxxxxxx>   <http://printf.net/>
One Laptop Per Child
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