On 2 May 2012 13:19, Jaehoon Chung <jh80.chung@xxxxxxxxxxx> wrote: > On 05/02/2012 04:01 PM, Kyungmin Park wrote: > >> Hi, >> >> On 5/2/12, Thomas Abraham <thomas.abraham@xxxxxxxxxx> wrote: >>> The instantiation of the Synopsis Designware controller on Exynos5250 >>> include extension for SDR and DDR specific tx/rx phase shift timing >>> and CIU internal divider. In addition to that, the option to skip the >>> command hold stage is also introduced. Add support for these Exynos5250 >>> specfic extenstions. [...] >>> @@ -265,6 +266,10 @@ static u32 dw_mci_prepare_command(struct mmc_host *mmc, >>> struct mmc_command *cmd) >>> cmdr |= SDMMC_CMD_DAT_WR; >>> } >>> >>> + if (slot->host->drv_data->ctrl_type == DW_MCI_TYPE_EXYNOS5250) >>> + if (SDMMC_CLKSEL_GET_SELCLK_DRV(mci_readl(slot->host, CLKSEL))) >>> + cmdr |= SDMMC_USE_HOLD_REG; >> Some other board, custom SOC also can use this HOLD register. So it's >> not EXYNOS5250 specific one. I think we introduce the more generic >> quirks for this instead of SOC specific. > > One more, I think that also need to check the IMPLEMENT_HOLD_REG bit in HCON register. > It has dependency with that. The above code is specific to Exynos5250 and hence it is not required to check the IMPLEMENT_HOLD_REG bit in HCON register. On Exynos5250, the hold register is implemented and available. > As Mr.Park is mentioned, this register is clock phasing. > In spec, card is enumerated in SDR12 or SDR25 mode, the application must program the use_hold_reg. Exynos5250 hardware manual specifies additional restrictions on the use of hold register. The above code checks for those restrictions and programs the USE_HOLD_REG accordingly. Please let me know if there is any condition that is not handled by the above code. Thanks, Thomas. > > Best Regards, > Jaehoon Chung > -- To unsubscribe from this list: send the line "unsubscribe linux-mmc" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html