RE: [PATCH] SD/MMC: fix the issue of SDHC performance regression

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>-----Original Message-----
>From: Liu Qiang-B32616
>Sent: Monday, November 07, 2011 5:36 PM
>To: linux-mmc@xxxxxxxxxxxxxxx
>Cc: cjb@xxxxxxxxxx; Li Yang-R58472; Gala Kumar-B11780; Liu Qiang-B32616
>Subject: [PATCH] SD/MMC: fix the issue of SDHC performance regression
>
>Low performance of SDHC (half of before) due to its frequency was set to
>25MHz,
>but not 50MHz (involved by commit id
>013909c4ffd16ded4895528b856fd8782df04dc6,
>add support for query function modes for uhs cards according to Physical
>Layer
>SPEC V3.01).
>
>Set high speed max frequency according to response status of CMD6, but
>not for SPEC Version. Response of switch command is first consideration
>factor when set SDHC max working frequency. TRAN_SPEED in CSD register
>will be seemed as the second factor.

I'm curious why many SD cards are not setting the clock frequency correctly in the CSD register.  Anyone has a clue?

- Leo


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