Re: [PATCH] sdhci: pxav3 controller needs 32 bit ADMA addressing

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Hi Philip,

On Mon, Jul 11 2011, Philip Rakity wrote:
> enable the quirk.
>
> Best used in conjunction with patch downgrading
> ADMA to SDMA when transfer is not aligned.
>
> Signed-off-by: Philip Rakity <prakity@xxxxxxxxxxx>
> ---
>  drivers/mmc/host/sdhci-pxav3.c |    3 ++-
>  1 files changed, 2 insertions(+), 1 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c
> index 4198dbb..fc7e4a5 100644
> --- a/drivers/mmc/host/sdhci-pxav3.c
> +++ b/drivers/mmc/host/sdhci-pxav3.c
> @@ -195,7 +195,8 @@ static int __devinit sdhci_pxav3_probe(struct platform_device *pdev)
>  	clk_enable(clk);
>  
>  	host->quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
> -		| SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC;
> +		| SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
> +		| SDHCI_QUIRK_32BIT_ADMA_SIZE;
>  
>  	/* enable 1/8V DDR capable */
>  	host->mmc->caps |= MMC_CAP_1_8V_DDR;

Pushed to mmc-next for 3.1 with Zhangfei's ACK, thanks.

- Chris.
-- 
Chris Ball   <cjb@xxxxxxxxxx>   <http://printf.net/>
One Laptop Per Child
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