>From 510b7871a7613ef56fd5f7818415d6c0c85ad7dc Mon Sep 17 00:00:00 2001 From: Philip Rakity <prakity@xxxxxxxxxxx> Date: Mon, 20 Dec 2010 21:51:51 -0800 Subject: [PATCH] sdhci: add support for H/W clock gating of SD controller MMP2 controller allows clock gating for SD/eMMC/SDIO cards by extending the definition for SDCTRL_2_ASYNC_INT_EN in the host control register 2. The SD Host Controller spec defines this bit (14) for use with SDIO. Use standard values in sdhci.h for register. Signed-off-by: Philip Rakity <prakity@xxxxxxxxxxx> Signed-off-by: Mark F. Brown <markb@xxxxxxxxxxx> Tested-by: Philip Rakity --- drivers/mmc/host/sdhci-mmp2.c | 5 ++--- 1 files changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/host/sdhci-mmp2.c b/drivers/mmc/host/sdhci-mmp2.c index 6824177..7303421 100644 --- a/drivers/mmc/host/sdhci-mmp2.c +++ b/drivers/mmc/host/sdhci-mmp2.c @@ -39,7 +39,6 @@ #define DRIVER_NAME "sdhci-mmp2" -#define HOST_CTRL_2 0x3E #define ASYNC_INT_EN (1 << 14) #define SD_CFG_FIFO_PARAM 0x100 @@ -148,9 +147,9 @@ static void programFIFO(struct sdhci_host *host, int enable) tmp = readw(host->ioaddr + HOST_CTRL_2); if (enable) - tmp |= ASYNC_INT_EN; + tmp |= SDCTRL_2_ASYNC_INT_EN; else - tmp &= ~ASYNC_INT_EN; + tmp &= ~SDCTRL_2_ASYNC_INT_EN; writew(tmp, host->ioaddr + HOST_CTRL_2); } -- 1.6.0.4
Attachment:
0021-sdhci-add-support-for-H-W-clock-gating-of-SD-contro.patch
Description: 0021-sdhci-add-support-for-H-W-clock-gating-of-SD-contro.patch
