2010/9/1 Richard Zhu <r65037@xxxxxxxxxxxxx>: > The FSL's eSDHC have one 32bit register that combine the two > 16bit Transfer Mode and Command registers. > Add this quirk to let SW driver to support FSL's eSDHC. What happens if you do this for every SDHCI host? Is there one that breaks if changing the two registers are combined into single 32-bit write? Best Regards, Michał Mirosław -- To unsubscribe from this list: send the line "unsubscribe linux-mmc" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
